STRAINED SOI

APRIL 2005 – FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING STRAINED SOI FOR SUB-65-NM DEVICES

Freescale and Soitec Group announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in electron mobility, as well as high compatibility with existing SOI CMOS processes, the collaborative effort demonstrated that 45-nm CMOS devices built using strained SOI substrates can effectively take device performance to the next level— ultimately enabling Freescale to bring faster, more power-efficient next-generation chips to market. •

SEMICON WEST 2005: CELEBRATING A DECADE OF SMART CUT™

Smart Cut™ technology made its world debut in 1995, when Soitec founder André-Jacques Auberton-Hervé announced it at Semicon West. As we mark this ten-year anniversary, consider what has been achieved thanks to a decade of Smart Cut. Now supported by a portfolio of over 1000 patents worldwide, millions of chips are produced every year using Smart Cut enabled SOI substrates. The technology is proving incredibly versatile, addressing new materials, new markets, and paving the way to new end-products.
Happy Anniversary! •

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