Strain and SOI Lead to Faster, Cooler Transistors


Applied Materials responds to evolving requirements.

Prior to 65nm device manufacturing, performance improvements from one generation to the next have been gained primarily through continuous reduction of transistor dimensions. However, for the 65nm generation and below, following this approach without change leads to unacceptably high leakage and power consumption. To help navigate this formidable challenge and continue enhancing device performance, IC manufacturers are adopting new methodologies, processes, and materials. Key among the advanced technologies that contribute to faster transistor speeds with reduced leakage are strained silicon and silicon-on-insulator (SOI).

Strained silicon engineering promotes the fabrication of faster transistors without the need to physically reduce device dimensions, thereby avoiding the excessive leakage currents traditionally seen with ultra-small features. This technology is already in production in a variety of forms and has proven very beneficial to 65nm node development. Approaching the challenge from another direction, the embedded insulating layer in a SOI substrate reduces junction capacitance and increases carrier mobility, allowing devices to run faster and use less power. SOI has, for example, resulted in transistor performance increases of 25-35% and average power consumption reductions of 40-50% over its more commonly used bulk silicon substrate counterpart.

From a capital equipment supplier’s standpoint, the perspective is slightly different. Not only must the system precisely control the processes used to fabricate these strained silicon structures and SOI substrates, but it must do it reliably and repeatedly at an acceptable cost per wafer. With newly designed vacuum batch wafer load locks engineered to minimize ambient exposure for interface layer management, and with up to four chambers on one mainframe for high throughput, Applied Materials’ market share leading epitaxial CVD systems are uniquely designed to meet these requirements.

The continual pursuit of better device performance has led to a multitude of improvements and innovations over the years. Faster, cooler transistors fabricated with the use of strained silicon and SOI are just two of the advanced technologies allowing the industry to keep on pace with Moore’s law. •

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