Fab Floor Tip: Running SOI in RTP

A quick guide to successful rapid thermal processing of SOI wafers

Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI?

First, the layer stack of an SOI wafer has a different reflectivity spectrum than a bulk wafer. It absorbs less lamp radiation than bare silicon.

Second, SOI has a crown. This non-SOI region at the edge of the wafer behaves as bulk. Constraints may appear during RTP due to an imbalance in temperature between the center and the very edge of the wafer. Dopant activation may vary from the center to the edge and affect device performance. Eventually, slip lines could appear.
Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI?

First, the layer stack of an SOI wafer has a different reflectivity spectrum than a bulk wafer. It absorbs less lamp radiation than bare silicon.

Second, SOI has a crown. This non-SOI region at the edge of the wafer behaves as bulk. Constraints may appear during RTP due to an imbalance in temperature between the center and the very edge of the wafer. Dopant activation may vary from the center to the edge and affect device performance. Eventually, slip lines could appear.

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