Enhanced Strained Silicon-On-Insulator CMOS Devices

Freescale has investigated a selective biaxial-uniaxial strain hybridization method that significantly enhances drive current without adding process complexity.

It has become increasingly difficult to scale CMOS transistors, yet still maintain high drive currents and simultaneously reduce supply voltage (Vdd). This is because threshold voltage and gate oxide thickness cannot be scaled at the same rate as Vdd without leakage current exceeding stand-by power requirements. Thus, transistor scaling rapidly reduces the maximum gate overdrive factor.

At the same time, higher channel doping concentrations and more abrupt, shallower source-drain junctions have been used to control short channel effects at very short gate lengths. These factors cause detrimental effects to the transistor, such as degraded carrier mobility, higher dopant fluctuations, and increased series resistance. Therefore, much attention has been focused on high mobility channels that exhibit increased inversion layer mobilities and higher carrier velocities in short channel devices. Thus, even with reduced supply voltages, devices with increased channel mobilities exhibit higher drain current, allowing high-speed, low-power CMOS applications.

Channel mobility gain can be achieved with process-induced uniaxial stress, biaxial stress virtual substrates, modifying the surface and channel orientation, or material having high-mobility such as Ge, SiGe alloys, or III-V compound semiconductors.

Various stress configurations
Figure 1: Schematic showing various stress configurations and their associated stressors (A. Thean et al., IEDM 2005).

To date, uniaxial stressors have been successfully employed in production for boosting mostly PMOS performance, but it has been more difficult to gain NMOS performance at the same improvement rate. This resulted in changing the n:p ratio, which requires some device layout change.

Moreover, desired stress configuration for boosting performance of PMOS and NMOS is quite complicated as shown in Figure 1; therefore, using a uniaxial stress technique would increase process complexity/cost, cycle-time and it also requires additional capital and facility investment for production ramp.

Despite the increasing complexity, uniaxial strain techniques such as embedded SiGe or compressive nitride etch stop layer (cESL) for compressive stressor and tensile Nitride etch stop layer (tESL) have been implemented in manufacturing for 90 nm high-performance circuits.

Enhancing NMOS and PMOS performance to retain the same n:p ratio is desirable for minimum disruption and speeding new technology introduction. Strained Silicon- On-Insulator (sSOI) substrates provide a 1.5–2.5 GPa biaxial tensile strain directly in the device channel region, further boosting device performance. The sSOI substrate can function as a strain platform to attain higher channel stress when combined with processinduced stressors.

TEM cross section
Figure 2: TEM cross-section showing the integration of eSiGe and cESL stressors for a sSOI pFET (A. Thean et al., VLSI 2006).

Through a novel method of selective biaxialuniaxial strain hybridization, a scalable enhanced sSOI CMOS technology has been demonstrated as shown in Figure 2. With this mixed-strain approach, NMOS uniaxial strain can be amplified by the substrate strain platform while sSOI PMOS can be enhanced beyond conventional single unaxially-strained or biaxially-strained silicon.

Figure 3 indicates that sSOI NMOS/PMOS drive current enhancements as high as 27%/36% have been achieved for sub-40 nm devices at 1V with 30% reduction in gate leakage current, while requiring minimum additional process complexity cost and capital investment for wafer manufacturers, but it adds premier substrate cost. Final die cost must be evaluated for making the strategic business decision.

Performance and scalability of sSOI devices and the advantages over pure biaxial and single uniaxial strained Si technologies have been demonstrated. Our development work has shown that using an sSOI substrate to combine the benefits of the SOI circuit and channel mobility enhancement meets the performance requirements of lower power consumption for portable electronics applications.

Short channel sSOI
Figure 3a: Short-channel sSOI NMOS enhancement, IDsat-Ioff (W=1μm) (A. Thean et al., VLSI 2006). Figure 3b: Short-channel sSOI PMOS enhancement, IDsat-Ioff (W=1μm) (A. Thean et al., VLSI 2006).


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