Embedded Memories in SOI

Embedded DRAM on SOI is set to proliferate at the 45nm node.

Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).

There are several driving forces for this transition:

• Larger caches that are electrically closer to high-speed, multi-core processors. A DRAM cell is 5-8 times smaller than an SRAM cell. At the functional level, DRAMs occupy 3-4 times less area per MB than SRAMs.

• Power – DRAMs tend to have leakage currents about 1000x lower than SRAMs on a per cell basis.

• Soft error rates, which are thousands of times lower in DRAMs.

• Greater cell stability for DRAMs, especially at lower voltages.

However, DRAMs add a bit more complexity than SRAMs to a logic chip, and the fastest DRAMs tend to be slower by a factor of 2-3. Therefore a typical processor IC will use a judicious combination of SRAM for the smaller-size, lower-level caches (where speed is important) and DRAMs for the larger-size, higher-level caches (where density is crucial).

Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).

The case for SOI

To date all eDRAM applications have been in bulk CMOS technology.

But as advanced processors migrate to SOI, there is a need to adapt eDRAM to SOI.

It is relatively straightforward to build a conventional DRAM cell in SOI and in fact for deep trench cells it is simpler. The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs as shown in Figure 1, where the buried oxide is used to completely isolate the capacitor plate from the device. (A stacked capacitor DRAM can also be fabricated in SOI though there is no cost advantage going to SOI.)

The migration of established DRAM technologies that have been proven over several generations in bulk promises to be the quickest and least risky way to embed DRAMs in SOI logic.

Figure 1. A cross section of a 45nm SOI trench cell.

In addition, there are several novel ideas that leverage SOI-specific effects such as the floating body and back gate interface. These offer the prospect of further simplification if they can be proven in production. We expect the use of eDRAM to proliferate to SOI in the 45nm generation.

Leave a Reply

Your email address will not be published. Required fields are marked *