SOI Substrates with Ultra-Thin BOX


Soitec is now sampling 25nm-thick UT-BOX.

Advanced SOI with ultra thin buried oxide (UT-BOX), in which the insulating BOX layer is less than 50nm thick, brings additional benefits to SOI CMOS architecture. It enables:

• electrostatic control of the device by back biasing, allowing ultra-low power operation through dynamic Vt control [1, 2].

• the definition of new memory device architectures such as capacitor-less one-transistor DRAM cells based on the floating body effect [2, 3].

• in combination with a FD MOSFET architecture, the potential elimination of the Vt fluctuation issue related to statistical dopant fluctuation (which at 45nm is cited as impacting SRAM stability).

To support the industry’s evaluation of UT-BOX SOI, a Soitec R&D effort is developing 300mm SOI wafers with BOX thickness ranging from 50nm down to 10nm. As with all of Soitec’s UNIBOND™ family of wafers, the UT-BOX SOI wafers are fabricated using Smart Cut™ technology.

UT-BOX development
In certain device architectures such as floating body memory cells or for back gate control, BOX plays an active role. In these cases, BOX characterization requires more specific attention both in terms of thickness uniformity and electrical oxide quality.

BOX uniformity of 1nm (on wafer min-max) has been attained. Buried oxide charge and buried interface quality are similar or better than mature SOI product. The breakdown field, which is a critical parameter for such thicknesses, is higher than 10MV.cm-1, typical for gate oxides of such thicknesses.

Soitec’s 25nm thick UT-BOX products currently under development will be commercially available in 2008, in time for the 45nm technology node. The defectivity monitoring curve in Figure 1 shows the learning curve with a typical defectivity at 0.15µm threshold lower than 0.15 def./cm². This quality allows us to sample R&D prototypes so that our partners can evaluate this technology both at the device and circuit level.

Customer feedback indicates that UT-BOX gives chipmakers additional “knobs” to further optimize device architecture and opens new areas of investigation.

In preparation for the 32nm node, early sampling of 10nm-thick UT-BOX is scheduled for the first half of 2007.

References:
1- Fenouillet-Beranger et al., Solid-State Electronics 48 (2004)
2- Tsuchiya et al. IEDM 2004
3- Shino et al., IEDM 2004
4- Minami et al., IEDM 2005

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