Conference Proceedings

International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
(April 2007):

Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI), Che-Hua Hsu, Weize Xiong, Chien-Ting Lin, Yao-Tsung Huang, Mike Ma1, C.R Cleavelin, Paul Patruno, Mark Kennard, Ian Cayrefourcq, Kyoungsub Shin, Tsu-Jae King Liu (UMC, Texas Instruments, Soitec, UC Berkeley), pp. 174-175.

Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies.  K. Schruefer, K. von Arnim, C. Pacha, J. Berthold, C. R. Cleavelin, T.Schulz, W. Xiong, and P. Patruno(Infineon Technologies, Texas Instruments, ATDF, Soitec)

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL, Collaert, R. Rooyackers, G. Dilliwaya, V. Iyengar, E. Augendre, F. Leys, I. Cayrefourq, B. Ghyselen, R. Loo, M. Jurczak and S. Biesemans (IMEC, University of Surrey, K.U. Leuven, ESAT-INSYS, University of North Carolina at Charlotte, Soitec)  , pp. 176-177.

ECS, Silicon-on-Insulator Technology and Devices 13, ECS Transactions, Volume 6, Issue 4, 2007 (Editors: G. Celler, S. Bedell, S. Cristoloveanu, F. Gamiz, B.Nguyen, Y. Omura):

Embedding Device Solutions in Engineered Substrates, Carlos Mazuré (Soitec), DOI: 10.1149/1.2728835.

SOI Metrology and Characterization in Modern Wafer Production, Oleg Kononchuk, F. Brunier, and M. Kennard (Soitec).  DOI: 10.1149/1.2728865.

Evaluation of different etching techniques in order to reveal dislocations in thick Ge layers, A. Abbadie, J.M. Hartmann, C. Deguet, L. Sanchez, F. Brunier, and F. Letertre (Soitec, CEA-LETI).

A Chromium-free Defect Etching Solution for Application on SOI, J. Mähliß, A. Abbadie and B. O. Kolbesen (JWG University, Soitec).

Complementary Single-Crystal Silicon TFTs on Plastic, H.-C. Yuan, Z. Ma, C. S. Ritz, D. E. Savage, M. G. Lagally, and G. K. Celler (U.Wisconsin, Soitec).

Instability of Threshold Voltage of Flexible Single-Crystal Si TFTs, H. Pang, H.-C. Yuan, M. G. Lagally, G. K. Celler (U.Wisconsin, Soitec).

Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications, Weize W. Xiong, C. Rinn Cleavelin, Che-Hua Hsu and Mike Ma, Klaus Schruefer, Klaus Von Arnim, Thomas Schulz, Ian Cayrefourcq, Carlos Mazure, Paul Patruno, Mark Kennard, Kyoungsub Shin, Sun Xin, and Tsu-Jae King Liu, Karim Cherkaoui, and J.P. Colinge (Texas Instruments, UMC, Infineon, Soitec, UC Davis, Tyndall National Institute).

VLSI Symposium, June 11-14, 2007, Kyoto,Japan

Fully Integrated VLSI CMOS and Photonics, (Plenary talk by C.Gunn, Luxtera)
The future direction of photonics, on SOI and integrated into CMOS circuits. As an example, a 40 Gbps transceiver is demonstrated.

SOI SRAM by ABC-technology for 32nm, (Y.Hirano, Renesas)
The active-body-biased (ABC) structure, where the body-bias is controlled through well-contact is applied to the SRAM cell. It was shown that ABC enhanced the static-noise-margin (SNM) by 27% for 32nm node, and 49% for 22nm node.

Multiple Stress Memorization in Advanced SOI CMOS Technologies, (A.Wei, AMD)
A new stress memorization technique (SMT)featuring source/drain amorphization plus low temperature was presented. It has the additive effect to the conventional high-temperature RTA-induced SMT in terms of drain current enhancement. It was ascribed to the stress localization to the source/drain regions, as a result of amorphization implantation.

Scalability of Direct Si Bonding (DSB) for 32nm node, (H.Yin, IBM)
Defect elimination at STI boundary is discussed with optimization of process sequence, (110) Si thickness, and 45-degree rotated (100) substrate. It is concluded that it is scalable down to 22nm with these countermeasures.

IEEE International SOI Conference (October 1-4, 2007, Indian CA,USA)

BEST PAPER AWARD:  High performance, highly reliable FD/SOI I/O MOSFETS in contemporary high-performance PD/SOI CMOS, V.P. Trivedi et al (ASTS, TSO, Freescale).

45nm SOI and beyond – getting to a general purpose technology, Subramanian Iyer (IBM plenary).

SOI based technology for smart power applications, P. Wessels (NXP plenary).

Analog and RF SOI circuits for low poer or harsh environment applications, L. Demeus (CISSOID plenary).

65nm CMOS Bulk to SOI comparison, J.L. Pelloie et al (ARM, UMC).

Integrated Inductors in HR SOI CMOS technologies:  on the economic advantage of SOI technologies for the inegration of RF applications, F.Gianesello et al (STMicroelectronics, CEA-LETI).

Linear cellular antenna switch for hightly-integrated SOI front-end, T. McKay et al (RFMD).

Physical IP for SOI design infrastructure, JL Pelloie (ARM, invited).

A Plasma Damage Mitigation Concept for SOI Technologies: Lightning Rods, M.Pelella et al (AMD).

Dual Silicide SOI CMOS Integration with Low-Resistance PtSI PMOS Contacts, S. Zollner et al (Freescale).

A Novel Two-Transistor Floating Body Memory Cell, J. Fossum et al (U.Florida, Freescale).

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET, W. Xiong et al (Texas Instruments, Central R&D, Soitec, Tydall National Institute, UC Davis).

Evaluation of FinFET RF Building Blocks, G. Knoblinger et al (Infineon, Technical U.Munich, IMMS, Texas Instruments, Soitec).

Study of Fin Profiles and MuGFETs built on SOI wafers,  P. Patruno et al (Soitec, CEA-LETI, Texas Instruments, Central R&D, UMC, Tyndall National Institute).

High hole mobility GeOI pMOSFETs with high K/metal gate on Ge condensation wafers, L. Clavelier et al (CEA/LETI-Minatec, STM, IMEP/INPG-Minatec).

Insights Into Gate-Underlap Design in FinFETs for Ultra-Low Voltage Analog Performance, A. Kranti et al (Northern Ireland Semiconducytor Research Centre, School of Electrical and Electronic Engineering).

Technology-Based FOM for High Voltage LDMOSFETs-Proof of Value of SOI in Power ICs, M.M. Iqbal et al(Engineering Dept, Cambridge University).

RF Lopwer NLDMOS Technology Transfer Strategy from 130nm to, the 65nm Node on thin SOI, O. Bon et al (STM, University de Toulouse, CEA-LETI).

Gate Controleed Bipolar Action in Ultrathin Body Dynamic-Threshold SOI MOSFET, Y Omura et al (Kansai University).

65nm CMOS Bulk to SOI comparison, R. Mishra et al (GeorgeMason University, IBM).

Circuit Performance Optimization in Advanced PD-SOI CMOS Development, W.T. Chiang et al (UMC, ARM).

3D Stacked Channels: How series resistances can limit 3D Devices Performance, E. Bernard et al (CEA-LETI, STM, NXP, INLINSA).

Innovative approach to drive floating body Z-RAM embedded momory to 32nm and beyond, D. Fisch et al (Innovative Silicon).

Analysis of Sensing Margin in Silicon-on-ONO (SOONO) Devive for capacitor-less RAM Application, E. J. Yun et al (Samsung).

SOI Devices and RO on Thin Dielectric Membrances for Pressure Sensing Applications, B. Olbrechts et al (Universite Catholique de Louvain, Concordia University).

Flexfet™: Independently-Double-Gated SOI Transistor with Variable Vt and 0.5V Operation Achieving near Ideal Subthreshold Slope, D. Wilson et al (American Semiconductor Inc., Boise State University, Tennessee Tech University).

Multi-Gate SOI MOSFET operations in harsh environments, W.Xiong et al, (TI invited, Central R&D, Infineon, Tyndall, UC Davis, Soitec).

Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs, J. Song et al (UC San Diego, TI, Central R&D,UMC, Soitec).

SiGe and Ge Material, Processing and Devices Vol 3 N°7:

In situ HL etching and selective epitaxial growth of doped Ge for formation of recessed sources drains. J.M. Hartmann et al (CEA-LETI, STMicroelectronics).

Nanoscaled MOSFET transistors on Strained Si, SiGe & Ge layers: some integration and electrical features. T Ernst et al (CEA-LETI/IMEP).

Channel material Innovation for continuing the historical MOSFET Performance Increase. D.A. Antoniadis, A. Khakifirooz, I.Aberg, J.L.Hoyt (MIT).

Note: for more papers from last year’s ECS meeting, see the PaperLinks in ASN6.


AlGaN/GaN HEMTs on Epitaxies Grown on Composite Substrate, V. Hoel, S. Boulay, H. Gerard, V. Raballand, E. Delos, J.C. De Jaeger, M.A.Poisson, C. Brylinski, H. Lahreche, R.Langer, P.Bove (I.E.M.N, U.M.R-C.N.R.S, Alcatel-Thales III-V Lab, Picogiga International).  European Microwave Integrated Circuits Conference 2007 (Formerly GAAS®), Munich, 8-10 October 2007.

Nanomechanical Properties of strained Silicon-on-Insulator (SOI) Films epitaxially grown on
Si1-xGex and Layer Transferred by Wafer Bonding, Nathanael Miller, Kandabara Tapily, Helmut Baumgart, A. A. Elmustafa, George K. Celler and Francois Brunier (Old Dominion University, The Applied Research Center-Jefferson Lab, Newport News, VA, Soitec), MRS Proc. April 2007.

Flexible RF/Microwave Switch-PIN Diodes using Single-Crystal Si-Nanomembranes, H. Yuan, Z. Ma,  G. K.Celler, Proc. IEEE MTT-S  Intern. Microwave Symposium 2007 (Honolulu, Hawaii) paper WEP1B-11. (U.Wisconsin-Madison, Soitec)

A Merged MuGFET and planar SOI Process technology, Andrew Marshall, C. Rinn Cleavelin, Weize Xiong, Christian Pacha, Gerhard Knoblinger, Klaus Von Armin, Thomas Schulz, Klaus Schruefer, Ken Matthews, Wolfgang Molzer, Paul Patruno, Christian Russ.  IEEE International SOC Conference (September 26-28, 2007, Hsinchu, Taiwan).  (TI, Infineon, ATDF, Soitec).

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