Sony is investigating sculpting the waveguide between two layers of buried oxide.
The mainstream of microprocessor research activities has recently moved from increasing clock speed to multiplexing the number of microprocessors. Therefore, communication technology between microprocessors is of great interest in obtaining performance advantages.
Figure 1 shows a cross-sectional photograph of a double-SOI waveguide. The double-SOI waveguide is an optical waveguide located just underneath the surface: more specifically between two buried oxide (BOX) layers in an SOI substrate. The surface silicon above the waveguide has almost the same surface silicon characteristics as standard SOI wafers for CMOS.
Waveguides & real estate
The double-SOI waveguide is like a subway under the city of transistors: it can make communication pathways without consuming the precious surface real estate needed for CMOS devices.
The purpose of my research is to make double- SOI-waveguide technology better suited for CMOS. Consequently my goal is two-fold:
- to create optimal conditions for a low propagation-loss optical waveguide, and
- to ensure low crystal-defect conditions on the surface above the waveguide in order to realize electric and photonic integrated circuits (EPICs).
Figure 2 shows the process steps of three-dimensional (3D) sculpting technology used to fabricate double-SOI waveguides.
Starting with a bonded SOI wafer, this technology uses oxygen ion implantation to create a second BOX layer with different depths. The oxygen ion implantation is through a SiO2 mask, thereby carving out a ridge-type optical waveguide from a thicker section of the silicon layer sandwiched between the two BOX layers.
The 3D sculpting by oxygen implantation technology was developed at the laboratory of Professor Bahram Jalali of the University of California at Los Angeles while I was a visiting scholar.
Double-SOI-waveguide technology has benefits not only in a combination with CMOS devices but also in a combination with surface optical waveguides. In this latter case, it creates 3D optical circuits that have a high degree of availability for layout design compared to planar circuits.