SOI at UMC

With a full 65nm PDK in place for SOC designers, initial analysis indicates that SOI offers significant power savings and speed boost.

UMC’s recent announcement of a successful test chip built with ARM SOI libraries on our 65nm SOI process is a promising development for SOC designers. A full process design kit is now in place and ready for their use.

Initial circuit analysis indicates that a design built on SOI can save up to 20 percent in area and 30 percent in power consumption, compared to a part produced to reach the same performance on bulk CMOS at 65nm. SOI technology also offers up to 28 percent speed boost with 10 percent power reduction over bulk CMOS.

The test chip consists of a set of ARM physical IP that uses a standard cell library, an I/O library and a single-port SRAM memory compiler. This tape-out paves the way to mainstream adoption of SOI technology for improved speed and power in complex SOCs.

ARM aligned with UMC on its SOI efforts – deriving an SOI version of its existing bulk 65nm CMOS L65SP—by providing the specific modules required to develop and qualify the process, including design rules, electrical characterization of the devices and modeling for circuit simulation. The resulting L65SOI process features nominal 1V multi-threshold voltage thin gate oxide transistors, nominal 2.5V thick gate oxide transistors for I/O and a nominal 1V 0.62 square-micron 6-transistors SRAM bitcell.

The ARM standard cells used in the test chip support multi-VT and multi-power supply circuit designs. The I/O is 3.3V signal tolerant and the memory compiler is optimized for high-speed and low-power consumption.

We look forward to working with our customers as they assess SOI technology and begin the pilot projects that can herald a new era in mobility.

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