SilOnIS Awarded for Excellence


Fifteen partners participating in the program recognized for highly successful collaboration on strained SOI.

Peter Storck of Siltronic (left) and Bruno Ghyselen of Soitec (right) accepted the Noblanc award on behalf of the SilOnIS team during a gala dinner at Budapest’s Museum of Fine Art. (Courtesy: Medea+).

The European research program SilOnIS, which focused on strained SOI (sSOI), has been honored with the Jean-Pierre Noblanc Award for Excellence. The award is given each year in recognition of the most innovative and sustainable project carried out in the Eureka Medea+ microelectronics cluster of R&D programs.

SilOnIS (which stands for strained silicon-oninsulator substrates for high performance ICs, project number 2T101) was 36-month project completed in December 2007. Participants included (listed alphabetically): Aixtron, AMD Saxony, ASM, CEA-LETI, Freescale, FZJJuelich, Jobin Yvon, MPI-Halle, Nanometrics, NXP, OMI, Siltronic, Soitec, Sopra, and STMicroelectronics.

“Close collaboration between advanced substrate manufacturers and chipmakers was essential to match the developments in the two complementary fields,” observed Bruno Ghyselen of project leader Soitec.

The project developed high-volume fabrication technology for strained SOI wafers, guided by device evaluation, and supported by specific metrology. This enables the foundation of European industrial sourcing for large-diameter, advanced sSOI wafer substrates for the semiconductor industry. sSOI substrates are targeted at leading edge CMOS technology nodes requiring high-speed performance and/or very low-power consumption.

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