CEA-LETI reports on FD-SOI technology developed for the 32nm node and beyond.
A Fully Depleted SOI CMOS technology has been developed at CEA-LETI for Low Power applications at 32nm nodes and below.
For years, fully depleted devices have been considered as electrostatic boosters due the fact that they benefit from smaller short channel effects than regular Bulk devices.
In addition to the classic SOI advantages (full electrical isolation, smaller parasitic capacitances, steeper subthreshold swing), with FD-SOI dopant atoms are no longer necessary in the channel region to control the punchthrough between source and drain.
Intrinsic channel transistors can thus be used when combined with high-k gate dielectric and single mid-gap metal gate, leading to threshold voltages compatible with Low Power technology.
The removal of dopant atoms in the channel region appears as a key advantage in reducing variability issues that kill SRAM stability for sub-45nm nodes.
Solves key issues
Access resistance issues, historically considered as the main drawback of such technology, can also be easily eliminated through the use of selective epitaxy growth of silicon in the source/drain regions. Resistance values comparable to Bulk technologies can thus be obtained, enabling a competitive ION(IOFF) trade-off.
Lowers gate leakage by 1000x
Compared to regular sub-45nm bulk devices, FD-SOI technology gives us:
- 1000 times lower gate leakage current
- Subthreshold swing of 75mV/decade for 25nm long channel devices
- The smallest variability data (AVT<3mV.µm) ever reported on 25nm long channel devices.
- The possibility of using strained SOI material that boosts the NMOS drive current by 30% and that can be combined with classical stressor technologies to address high performance applications.