How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout.
The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio.
Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they can be coded in a straightforward manner using the Calibre user-friendly rule definition language and rule writer interface. Customers can simply augment their bulk CMOS rule decks by adding specific rules for SOI.
The same applies to LVS (layout versus schematic) checks and device and extraction models—variations for process types and CDs (critical dimensions) can all be easily defined in flexible Calibre rules. For example, SOI requires a different approach to parasitic capacitance modeling, and these are easily handled within Calibre xRC rule decks.
The benefit for process developers is that they see the same physical verification flow, the same tool look and feel, the same rule language, and the same use model whether they are working with SOI, bulk CMOS or any other technology.
For designers using the verification tools, the differences between CMOS and SOI are transparent, so there is no learning curve or flow disruption.
Designs that yield well
As we move into smaller geometries, the verification checks will become even more complex and more demanding in terms of accuracy.
We are seeing much bigger swings between designs that yield well and designs that yield poorly due to greater manufacturing sensitivity to specific feature shapes and patterns. To address these issues the Calibre platform is introducing new capabilities such as Equation-based DRC (design rule checking) and Advanced Device Parameters (ADP).
Equation-based DRC allows users to define rules as continuous 3-D functions that directly model the underlying physical effects.
For complex interactions common at small geometries, this is far more convenient and accurate than creating large tables of linear approximations involving many variables. ADP extends the flexibility and accuracy of device models to handle new interactions that occur as CD shrinks below 45nm, resulting in improved extraction accuracy.