Chip Designers: Having It All

With SOI, the performance-power trade-off can be balanced without changing design methodology.

If you’re a chip designer, what would it mean if you could measurably increase performance while keeping the same power consumption? Or, if you could meaningfully lower power consumption while retaining the same performance level? And what if you could do either one without changing methodology?

You might be really surprised.

But a growing design and manufacturing ecosystem that fosters mainstream design using SOI has begun to offer design teams exactly these benefits. The added performance and power reduction of SOI vs. bulk silicon, once the province of a few skilled, near-custom design teams, is becoming accessible to anyone using a mainstream commercial digital design flow today.

What’s different?

You might wonder: doesn’t SOI have different physical characteristics from bulk silicon, thus requiring special capabilities in EDA tools and flows? The answer is yes and no. SOI’s differences do drive some additional needs in EDA tools that work at the process, transistor, and geometry level.

TCAD must understand SOI recipes, circuit simulation requires specialized SPICE models plus specialized extraction for SOI device parasitics, and foundries need to supply DRC rule decks that include SOI rules.

Same design flow

At the gate level, though, carefully constructed and validated physical IP can abstract away virtually all of the SOI differences, while letting the natural circuit-level speed and power advantages of SOI shine through.

Clever circuit design coerces SOI gates to behave almost the same as bulk silicon gates, albeit faster. Intelligent characterization reshapes the remaining vestiges of SOI variance like the “history effect” into standard process corner data that can be exploited throughout implementation and sign-off via the Synopsys’ Galaxy™ Design Platform, with only the most minimal changes in flow.

As the SOI ecosystem fills out with a complete catalog of well-designed and characterized SOI physical IP, design teams can embrace the advantages of SOI using their current, productive design flows and experience.

Synopsys and our partners are ready to help both mainstream and leading edge designers build and verify SOI-based chips.

SOI in Galaxy Flow © 2007 Synopsis, Inc.

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