Recent Conference Proceedings

May 2008, Hsinchu, Taiwan

Defect Delineation and Characterization in SiGe, Ge and other Semiconductor-on-insulator Structures. (Invited) Alexandra Abbadie, F. Allibert, F. Brunier (Soitec)

Performance and Scaling of cMOSFETs on Ultra-Thin Strained SOI. (Invited) Francois Andrieu, V. Barrel, T. Poiroux, O. Faynot, S. Deleonibus (CEA-LETI Minatec)

Spectral Responsivity of Fast Ge Photodetectors on SOI. Mathias Kaschel, M. Kaschel, M. Oehme, O. Kirfel, J. Lupaca-Schomber, E. Kasper (Universitat Stuttgart)

May 2008, Phoenix, Arizona, USA

Material Aspects and Challenges for SOI FinFET Integration (E1 636, Invited)

M. J. Van Dal, G. Vellianitis, R. Duffy, B. Pawlak, K. Lai, A. Hikavyy, N. Collaert, M. Jurczak and R. Lander (NXP, TSMC, IMEC)
This paper elaborates on the key material aspects of front-end-of-line SOI trigate FinFET integration with high fin aspect ratio. It shows that the formation of low resistive contacts including extension, selective epitaxial growth (SEG) on the fin source/drain areas, optimized source/drain implants and silicidation conditions are paramount to achieve low access resistance and high drive currents.

Ge Enrichment Technique on SiGe/SOI Mesa Islands: a Localized GeOI Structures Fabrication Method (E1 637)
B. Vincent, J. Damlencourt, Y. Morand, D. Rouchon and M. Mermoux (CEA, STMicroelectronics, INPG)
The paper says that to be advantageous, GeOI structures need to be confined within pMOSFET channels or limited to active zones available for pMOSFETs. It proposes for the first time an identification of all mechanisms induced in this technique, limitations highlights and improvements proposals. The local Ge enrichment technique consists of a selective Si oxidation of a SiGe/SOI mesa island previously etched to the BOX. The authors propose a review of all mechanisms involved in the local Ge enrichment techniques, and conclude that strain engineering is necessary on initial structures to get final homogeneous Ge enriched mesa islands.

Hole Mobility Behavior in Strained SiGeon-SOI p-MOSFETs (E1 656)
T. Shim, S. Kim, J. Baek, H. Lee, G. Lee, K. Kim, W. Cho and J. Park (Nano-SOI Process Lab, Hanyang University, Kwangwoon University, South Korea)
This study investigates the hole mobility behavior in a compressive strained SiGe layer grown on SOI, depending on effective electric fields, Eeff , by varying Ge concentrations.

Silicides for 32nm and Beyond (E673)
P. R. Besser, C. Murray and C. Lavoie (AMD, IBM)
This presentation shows the silicide engineering advantages of incorporating alloying elements with Ni, and highlights the manufacturing challenges of NiSi, improving morphological stability enhancing the device performance and yield of high-performance SOI technologies for microprocessors, for example.

May 2008, Strasbourg, France

Evolution of end-of-range defects in silicon-on-insulator substrates.
From the EU IST ATOMICS project team: P.F. Fazzini, F. Cristiano, C. Dupré, S. Paul, T. Ernst, H. Kheyrandish, K.K. Bourdelle, and W. Lerch. (Fraunhofer, CNRS, CSMA, Mattson, ST, Synopsys, U.Newcastle and Soitec).

June 2008, Grenoble, France

Low-Voltage Scaling Limitations of Nano-Scale CMOS LSIs (tutorial).
This tutorial describes low-voltage scaling limitations of nano-scale CMOS LSIs , focusing on specific circuit blocks such as logic gates, SRAM cells, and DRAM sense amplifiers. Possible solutions to drastically reduce Vmin are presented and evaluated. They are repair techniques, new MOSFETs (such as metal-gate bulk and metal-gate FD-SOI), and low-VT dynamic circuits. Kiyoo Itoh (Hitachi).

Fully Depleted SOI devices for Low Power technologies (invited)
O.Faynot (CEA)

CMOS SOI technology for WPAN Application to 60Ghz LNAs (invited)
A. Siligaris, C. Mounet, B. Reig, P. Vincent, A. Michel (CEA-Leti, ANSOFT).

SRAM Memory Cell Leakage Reduction Design Techniques in 65nm Low Power PD-SOI CMOS
Olivier Thomas, Marc Belleville, Richard Ferrant; (CEA, Minatec, ST)

An SOI-based Self-aligned Quasi-SOI MOSFET with Π-shaped Semiconductor Conductive Layer
Yi-Chuen Eng, Jyi-Tsong Lin, Shiang-Shi Kang (National Sun Yat-Sen University, Taiwan)

SOI Chip Design and Charging Damage (invited)
Terence B. Hook (IBM)

June 2008, Monterey, CA, USA

Fracture Mechanism in Hydrogen Implanted Germanium
F. Mazen,; A.Tauzin, L. Sanchez, F. Chieux, C.Deguet, , France; E. Augendre, C, France; C. Richtarch,; T. Akatsu,; L. Clavel, (CEA-Leti-Minatec, Soitec)

Layer Transfer with Implant induced Defects: A Path to Advanced Engineered Substrates (invited)
K.K. Bourdelle (Soitec)

Automotive SOI-BCD Technology Using Bonded Wafers (invited)
H. Himi, S. Fujino (Denso)

Comparison of Dopant Activation and Diffusion for Varying B Doses and PAI Conditions in Preamorphized Si and SOI
K.J. Kirkby (University of Surrey, UK)

A Comparative Study of Interaction of the End of Range (EOR) Defect Band with the Upper Buried Oxide (BOX) Interface for B and BF2 Implants in SOI and Bulk Si With and Without a Pre-amorphising Implant
A. J. Smith, J.J. Hamilton, B. Colombeau, R.P. Webb, R.M. Gwilliam, J. Sharp, K.J. Kirkby, M. Kah, (U. Surrey, UK; Chartered)

June 2008, Honolulu, Hawaii, USA

Technology Session 2 — FinFET and Multi-Gate MOSFETs
Novel Integration Process And Performances Analysis Of Low Standby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) On SOI With Metal / High-K Gate Stack
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Barral, V. Maffini-Alvaro, F. Andrieu, C. Vizioz, Y. Campidelli, P. Gautier, J.-M. Hartmann, R. Kies, V. Delaye, F. Aussenac, T. Poiroux, P. Coronel, A. Souifi, T. Skotnicki, S. Deleonibus (CEA-Leti-Minatec, STMicroelectronics, INL-INSA)
This paper reports on work on SOI with a Metal / high-K Gate stack leading to the best ION/IOFF ratios ever reported: 1.4×108 (0.8×108) for 50nm n- (p-) MCFETs. The authors show, based on specifically developed integration process, characterization methods and analytical modeling, how this performance is obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Technology Session 9 – Highlights
A Scaled Floating Body Cell (FBC) Memory with High-k +Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond
I. Ban, U. Avci, D. Kencke, P. Chang (Intel)
A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-microAmp sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at the 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Technology Session 17 – Advanced SOI
Smallest Vth Variability Achieved by Intrinsic Silicon on Thin BOX (SOTB) CMOS with Single Metal Gate
Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, S. Kimura (Hitachi, Renesas)
“Silicon on thin BOX” (SOTB) achieved the smallest Vth variability. The Pelgrom coefficients were 1.8 (NMOS) and 1.5 (PMOS), even in the case of relatively thick EOT of 1.9 nm. In this SOTB, multi-Vth control and suppression of short-channel effects were performed by adjusting the impurity concentration beneath the BOX keeping the channel almost intrinsic. The scalability of the SOTB is shown.

Selenium Co-implantation and Segregation as a New Contact Technology for Nanoscale SOI N-FETs Featuring NiSi:C Formed on Silicon-Carbon (Si:C) Source/Drain Stressors
H.-S. Wong, F.-Y. Liu, K.-W. Ang, S.-M. Koh, A.T.-Y. Koh, T.-Y. Liow, R.T.-P. Lee, A.E.-J. Lim, W.-W. Fang, M. Zhu, L. Chan, N. Balasubramaniam, G. Samudra, Y.-C. Yeo (National University of Singapore, Institute of Microelectronics, Singapore)
The paper reports a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height ФBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low ФBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with and without Se segregation. When integrated in nanoscale SOI n-FETs with Ni-silicided Si:C S/D, the new Se-segregation contact technology achieves 36% reduction in total series resistance and 32% ION enhancement. Linear transconductance GML in also shows large enhancement in the sample with Se-segregated contacts.

Mobility Of Strained And Unstrained Short Channel FD-SOI Mosfets: New Insight By Magnetoresistance
M. Casse, F. Rochette, N. Bhouri, F. Andrieu, D.K. Maude, M. Mouis, G. Reimbold, F. Boulanger, (CEA-Leti-Minatec, CNRS-GHMFL, IMEP CNRS/INPG/UJF)
Electron mobility in strained and unstrained FD-SOI MOSFETs is deeply investigated in linear regime by careful magnetoresistance measurements down to 40nm gate length and 20K. This method differs from standard ones because: it does not require any data on the short channel gate capacitance and gate length; it is more accurate at low inversion charge; the temperature dependence of the Coulomb Scattering (CS) limited mobility is higher. Additional mobility scattering has been confirmed for short channel nMOS, and unambiguously identified as CS. A 50% mobility gain for strained Si MOSFETs is still observable even in this dominant CS regime.

On Implementation of Embedded Phosphorus-doped SiC Stressors in SOI nMOSFETs
Z. Ren, G. Pei, J. Li, B.F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J.W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, R. Pal, I. Lauer, D-G. Park, D. Sadana (IBM, AMD)
The paper reports a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. The authors identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the Stress Memory Technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

Ten years after – Has SOI finally arrived?
(Technology Rump Session) A similar panel held 10 years ago concluded that SOI has a performance advantage over bulk, but cost would be its main barrier for wide adoption. The 2008 panel asks if anything has changed and will it change in the next decade? Will SOI penetrate more market segments or disappear? Does further technology scaling require the migration to fully-depleted SOI? Panelists: M. Bohr, Intel; R. Mahnkopf, Infineon; G. Shahidi, IBM; C. Mazure, Soitec; E. Suzuki, AIST; D. Scott, TSMC; A. Kameyama, Toshiba; M. Usami, Hitachi.

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