Smaller Pixels, Brighter Pictures

ST’s 3-megapixel back-illuminated image sensor for digital cameras leverages SOI, direct wafer-level bonding and thinning technologies, improving 1.45 x 1.45 µm² pixel quantum efficiency over 60%.

To meet consumer demand for higher-quality digital cameras embedded in a widening array of mobile devices, designers need image sensors with very small pixels (higher resolution, smaller, cheaper and lower power) that maximize the available light.

In response, the image sensor industry is coming out with a new generation of back-illuminated CMOS image sensors. In contrast to the current generation of front-illuminated devices, the back-illumination scheme moves the electronics to the bottom of the stack, so the light enters the device unimpeded. While this enables high-quality pictures or video even under low light conditions and simplifies some aspects of the design (particularly of the metal layers), it also introduces cost-effective manufacturing challenges.

STMicroelectronics has demonstrated the feasibility of manufacturing 3-megapixel CMOS image sensors with a very small pitch (just 1.45µm x 1.45µm) in a back-illuminated design. We have attained a high quantum efficiency (QE) of >60%. The QE indicates the percentage of photons that are converted into electrons.

The back-illumination design starts with an SOI wafer. We evaluated several SOI thicknesses in order to find an optimal balance between QE and crosstalk.

Crosstalk quelled

In a back illumination scheme, you don’t have the problem of the electronics getting in the way of the light’s path; however, the electrons generated by the light still have to reach the photodiode. Different colored lights have different wavelength ranges; blue light for example, which has a short wavelength, is particularly tricky.

Figure 1. Thicker SOI layers are preferable: higher light absorption and higher QE.

The longer the photo-generated electrons have to travel, the greater the chance that they’ll diffuse into neighboring pixels, thereby increasing electrical crosstalk. A thicker SOI layer increases QE, but it also increases crosstalk – hence the need for finding the optimal balance. We have determined this balance in the context of a manufacturable product (see Figure 1)

Lowering dark current

Dark current is essentially leakage current that flows even when the device is not operating. It can really deteriorate image quality badly. As such, it is a challenge in all CMOS image sensors, whether you’re using front or back illumination. Dark current is linked to crystalline defects in the silicon. The quality of the wafer-bonding interface, especially between silicon and the oxide interface, is critical to diminishing dark current.
We have achieved a mean low dark current of 1e/s at 25°C due to dedicated frontside and backside process steps such as a p+ pinning layer and thermal treatment. Other parameters such as conversion gain, lag and temporal noise are comparable to state-of-the-art frontside image sensors.


In our back-illumination scheme, after the final metal layers are created, a passivation layer and subsequent wafer-bonding layer (WBL) are deposited. The WBL is planarized and a support wafer is bonded to the processed wafer, then thinned through a subsequent grind-back.

We have demonstrated the manufacturing feasibility, and are now concluding work related to further cross-talk reduction as well as color filter and micro-lens processing.

Image from a 3MP back-illuminated array with 1.45µm pixel pitch

With these image sensors embedded in the next generation of cell phone cameras, dark and fuzzy snapshots should soon be a thing of the past

Process flow

  • SOI wafer
  • CMOS image process
  • Wafer bonding layer (WBL) and preparation
  • Wafer bonding and backside grinding
  • Anti-reflective coating (ARC)
  • Pad opening
  • Color filters and micro-lens

Acknowledgements: Tracit Technologies for wafer bonding and thinning studies; the CEA-LETI process teams; and the STM front-end technology and manufacturing group.

Reference: “A 3 Mega-Pixel Back-illuminated Image Sensor in 1T5 Architecture with 1.45 μm Pixel Pitch.”, Francois Roy*, Perceval Coudrain*, Xavier Gagnard*, Josep Segura*, Yvon Cazaux*, Didier Herault*, Nicolas Virollet*, Norbert Moussy**, Benoit Giffard**, Pierre Gidon** (* FTM Imaging, STMicroelectronics, Crolles, France; ** CEA-LETI-MINATEC, Grenoble, France). 2007 International Image Sensor Workshop. Jens Prima

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