October 2008, New Paltz, NY, USA
Researchers from the world over gathered at the beautiful Mohonk Mountain House in upstate New York this fall to listen to over 50 excellent presentations. Hot topics included memory, reliability and optimization. A selection of some of the best follows below, with links embedded for easy access to the abstracts.
BEST PAPER AWARD:
A. Veloso, L. Witters, M. Demand, I. Ferain1, N. J. Son, B. Kaczer, Ph. J. Roussel, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer, S.Biesemans, M. Jurczak (IMEC, Samsung, K. U. Leuven)
MuGFETs with caps sandwiched in-between 2 metals (TiN or TaN) in the gate stack were studied for multiple-VTs CMOS applications, resulting in additional understanding on the caps diffusion mechanism, reliability behavior and integration implications. This addresses concerns with regard to the tuning options for narrow fins. It is compatible with 3D device architectures and suitable for high-density circuits at sub-32nm nodes.
BEST POSTER AWARD:
D. Bol, R. Ambroise, D. Flandre , J.-D. Legat (U. Catholique de Louvain)
The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional Vdd and static energy. This makes FD SOI with metal gate a strong candidate for sub-45nm robust and energy-efficient subthreshold circuits.
Das, Koushik; Bernstein, Kerry; Burns, Jeff; Gebara, Fadi; Shih-Hsien Lo,; Nowka, Kevin; Rao, Rahul; Rosenfield, Michael (IBM)
Going forward, variability and power management are very big and inter-related issues. This paper gives an overview of the power/variability challenges in sub-100nm CMOS. It illustrates several circuit, EDA and system level reliability techniques for building robust low-power systems. Finally, to optimally design extremely dense, multi-core chips with billions of transistors, the authors emphasize the need for an approach integrating technology development, VLSI design, design automation tools and micro-architecture.
Herrera, G. V.; Bauer, Todd; Blain, M. G.; Dodd, P. E.; Dondero, R.; Garcia, E. J.; Galambos, P. C.; Hetherington, D. L.; Hudgens, J. J.; McCormick, F. B.; Nielson, G. N.; Nordquist, C. D.; Okandan, M.; Olsson, R. H.; Ortiz, K.; Platzbecker, M. R.; Resnick, P.J.; Shul, R. J.; Shaw, M. J.; Sullivan, C. T.; Watts, M. R. (Sandia)
Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers in the mid-1990s to develop a radiation-hardened semiconductor process for sub-0.5μm geometries. The expertise they developed opened opportunities to improve other technologies. This paper presents a high-level description of their SOI process technologies that have enabled a novel devices and products, including an accelerometer, RF MEMS microresonators and contacting switches, integrated optics (low-loss Si waveguides, the smallest and lowest power micro-ring modulators and thermo-optic phase modulators/switches), and ion traps for quantum computing (along with other atomic physics device examples).
Cai, Jin; Ren, Zhibin; Majumdar, Amlan; Ning, Tak H.; Yin, Haizhou; Park, Dae-Gyu; Haensch, Wilfried E. (IBM)
This paper looks at the key challenges for SOI CMOS to achieve sub-100pA/µm leakage current, which is required for low-standby power applications. Recent 45nm data illustrates the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, the authors identify several unique SOI opportunities that can broaden its appeal to the low power market.
U. E. Avci, I. Ban, D. L. Kencke, and P.L.D. Chang (Intel)
The authors demonstrate a scaled planar FBC technology with undoped-body featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. They predict this FBC scaling will be feasible at the 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.
Makosiej, Adam; Nasalski, Piotr; Giraud, Bastien; Vladimirescu, Andrei;Amara, Amara (Technical U. Lodz, ISE Paris, UC Berkeley, Leti)
This paper describes two novel sub-32nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10–15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.
J. Basak, L. Liao, A. Liu, Y. Chetrit, H. Nguyen, D. Rubin, and M. Paniccia (Intel, Numonyx)
This paper talks about the developments in silicon photonic devices that exploit the inherent high refractive index contrasts achievable on an SOI platform. It focuses on the optical modulator that has been designed for speeds up to 40Gbps. It also describes the design and performance of a photonic integrated transmitter chip, which has been demonstrated to transmit at an aggregate data rate of 200Gbps.
M. Fulde, F. Kuttner, K. v. Arnim, B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, M. Becherer, D. Schmitt-Landsiedel, G. Knoblinger (Infineon, Technical U. Munich, IMEC)
The integration of A/D and D/A converters is very important for SoC applications. The authors present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current-steering D/A converter are shown. The achieved performance proves the ability of recent FinFET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching and analog behavior of FinFETs enables reduced circuit area compared to planar designs.
Nguyen, Q.T.; Damlencourt, J.F.; Vincent, B.; Loup, V.; Le Cunff, Y.; Gentil, P.; Cristoloveanu, S. (IMEP-INP, CEA-Leti)
The authors report on the successful fabrication of hybrid SOI-GeOI wafers. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole-mobility in Ge islands and high electron-mobility in Si islands. The data confirms that hybrid wafers are attractive for co-integrating pMOSFETs in Ge and nMOSFETs in Si.
C.K. Chen, N. Checka, B.M. Tyrrell, C.L. Chen, P.W. Wyatt, D.R.W. Yost, J.M. Knecht, J.T. Kedzierski, C.L. Keast; (Lincoln Labs, MIT)
Lincoln Labs established a 3D IC technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. 3DIC technology in the most recently completed run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers. This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determining the impact of 3D vias on ring oscillator performance, and demonstrating functionality of single and multi-tier circuits of varying complexity. The work was sponsored under a DARPA/Air Force contract.
D.-W. Kim, M. Li, K. Hwan Yeo, Y. Y. Yeoh, S. D. Suk, K. H. Cho, K. Oh, W.-S. Lee (Samsung)
This paper reports fabrication of twin silicon nanowire FETs on SOI with down to 25-nm TiN surrounding the gate and 8-nm silicon nanowires with high manufacturability. Improved device reliability includes the reduction of junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. High performance is also obtained: 1124μA/μm and 1468μA/μm at off current of 1nA/μm for NMOS and PMOS, respectively.
Kranti, Abhinav; Raskin, Jean-Pierre; Armstrong, G. Alastair (Queen’s U. Belfast, U. Catholique de Louvain)
This paper gives a detailed analysis on the impact of parasitic capacitances/resistances and fin geometry in FinFETs for RF applications. RF FinFETs should be designed with Tfin/Lg of 0.6 and AR of 3, along with minimal fin spacing of 50 nm to achieve higher ƒT and ƒMAX values. Although FinFET will always exhibit higher parasitics than an equivalent planar technology, reduction of RSD to ITRS target specification, together with a minimal fin spacing Sfin, results in significant improvement in RF figures of merit.
Alles, M. L.; Ball, D. R.; Massengill, L.W.; Schrimpf, R. D.; Reed, R. A.;Bhuva, B. L. (Vanderbilt U.)
The continued path on Moore’s Law has increased the concern about soft errors, even in terrestrial applications. Multiple device (multiple bit) interactions and upsets are now one of the major challenges of analysis and mitigation in bulk CMOS devices. This is perhaps the major advantage for SOI with respect to single event effects. New SOI devices, including the MugFETS and ZRAMs, present opportunities for additional detailed study of single event effects as the devices approach the mainstream. One of the interesting aspects of the ZRAM is the difference in data state vulnerabilities compared to the conventional bulk DRAMs. This paper examines single-event effects and implications for SOI CMOS.
T.P. Haraszti1, R. Pancholy, J. Choma, R. Schober, K. Hunt; (Microcirc, USC, NanoPower, USAF Research Lab)
In all of the seven main memory components, the use of the novel SOI-specific sense amplifiers, memory-cells, and logic gates, evinced exceptionally speedy operations. This made possible fabrication and tests of complete memories which feature 2.2 GHz operational speed, 10−l2 error/bit/day and 1 Mrad total dose hardness. The SOI memories can indeed provide substantially faster operations than their best bulk counterparts do.
C. Pastore, F. Gianesello, D. Gloria1, E. Serret, P. Bouillon, B. Rauber, Ph. Benech (STMicroelectronics, IMEP/LAHC)
High-performance on-chip inductors are key RF passive components for most RF circuits. This paper reports on a state-of-the-art inductor integrated in an advanced high resistivity (HR) SOI RF CMOS technology, using a double 3-μm thick back-end-of-the-line (BEOL) module. The inductor performance is comparable to those obtained in dedicated passive component technologies (Integrated Passive Device (IPD) on glass or RF substrates): a quality factor Q greater than 30 and current capability up to 57 mA/μm @ 125 °C. The results pave the way to the integration of the whole RF front-end module (which is currently served by GaAs technologies) in an advanced HR SOI CMOS technology.
Emam, M.; Vanhoenacker-Janvier, D.; Anil, K.; Ida, J.; Raskin, J.-P. (U. Catholique Louvain, Oki Electric)
At Zero-Temperature-Coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for Low-Power Low-Voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and Partially Depleted SOI MOSFETs with and without body contact are analyzed.
G. Hamaide, F. Allibert, S. Cristoloveanu (Soitec, IMEP-INPG MINATEC)
The thickness dependence of mobility in state-of-the-art SOI wafers is essentially an artefact due to the vertical field, stemming from surface charges and increasing as the film gets thinner. Various passivation treatments were used and combined; their impact on top surface and buried interface quality was studied separately. Excellent mobility values, above 650 cm2V−1s−1 for electrons and 200 cm2V−1s−1 for holes were achieved after FGA.
K. Romanjek, C. Le Royer, A. Pouydebasque, E. Augendre, M. Vinet, C. Tabone, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, L. Clavelier, X. Garros, G. Reimbold, N. Daval, F. Boulanger, S. Deleonibus; (CEA-LETI/MINATEC, Soitec).
The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of Germanium-On-Insulator pMOSFETs is shown using the Lim&Fossum model historically developed for fully depleted SOI devices. This method can be used as a simple and efficient way to monitor the influence of the process on top and bottom interface trap densities and can be used as a process optimization qualifier for GeOI devices.
S. Okhonin, M. Nagoga, C.-W. Lee, J.-P. Colinge, A. Afzalian, R. Yan, N. Dehdashti Akhavan, W. Xiong, V. Sverdlov, S. Selberherr, C. Mazure (Innovative Silicon, Tyndall National Institute, Texas Instrument Inc., TU Vienna, Soitec)
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.