Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco).

• Hitachi

Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation. N. Sugii, et al.

Silicon on Thin BOX (SOTB) for high-speed, low-power SOCs has the smallest Vth variation among all planar CMOS structures. Researchers have now found ways to reduce threshold voltage variation even further.

• Leti/ST/Soitec

High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding. O. Weber, et al.

Undoped FD-SOI architectures are extremely effective in controlling Vt variability. Variation in the thickness of the top silicon is found not to be a significant factor in Vt variation; rather, thinning the top silicon minimizes Vt fluctuations.

• IBM/Freescale/AMD

22nm Technology Compatible Fully Functional 0.1µm2 6T-SRAM Cell. B. S. Haran, et al.

Researchers from the IBM Alliance describe the world’s smallest fully functional SRAM memory cell. This work suggests that SRAM technology can be extended on planar SOI.

• Toshiba

Autonomous Refresh of Floating Body Cell (FBC). T. Ohsawa, et al.

The physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without a sense amplifier operation. Therefore, FBC can be used to realize static RAM without periodical refresh while retaining data.

• NXP/TSMC/IMEC

First Observation Of Finfet Specific Mismatch Behavior And Optimization Guidelines For SRAM Scaling. T. Merelle, et al.

Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. This study provides guidelines for SRAM design in a FinFET technology.

• STMicroelectronics

190V N-Channel Lateral IGBT Integration in SOI 0.35µm BCD Technology. M. Sambi, et al.

The integration of 190V N-Ch. LIGBT in SOI 0.35μm shrunk BCD technology is described. The novel device shows a very high saturation current and good HTRB robustness.

• AMD/U.Dresden

Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance Microprocessors. J. Hoentschel, et al.

Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65nm and 45nm PD-SOI CMOS technologies. Product-level implementation shows a speed benefit of 12%.

• U.Tokyo

Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature. J. Chen, et al.

Accurate electron mobility in nanowires on (110) SOI has been achieved by the split C-V method for the first time.

• Intel/Numonyx

Silicon Photonic Modulator and Integration for High-speed Applications (Invited). L. Liao, et al.

Researchers presented recent results of a silicon photonic integrated chip that is capable of transmitting data at an aggregate rate of 200Gb/s. This is a continuation of the SOI-based work that Ansheng Liu of Intel wrote about in ASN#8.

Leave a Reply

Your email address will not be published. Required fields are marked *