27-29 April 2009, Hsinchu, Taiwan
VLSI-TSA is a platform for technical exchanges and communications by experts from all over the world who are actively engaged in research, development, and manufacturing on VLSI technology, systems, and applications. It is sponsored by the Industrial Technology Research Institute in Taiwan. A PDF of program and abstracts is available here.
- Keynote speech: Dr. Rene Penning de Vries, CTO, NXP Semiconductors, “From Living Faster to Living Better”
- FDSOI CMOS with Dual Backgate Control for Performance and Power Modulation.
Jeng-Bang Yau, et al. (IBM)
The authors demonstrate, for the first time, modulation of power/performance of a ring oscillator fabricated on thin-BOX (buried oxide) FD (fully-depleted) SOI using independent backgate controls for nFET and pFET. The results suggest the backgate technology is an additional knob for power/performance optimization and variability control, and attractive for continued CMOS scaling.
- Highly Performant FDSOI pMOSFETs with Metallic Source/Drain
T. Poiroux, et al. (CEA-LETI/Minatec, STMicroelectronics)
This paper reports on the fabrication and the characterization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices.
- Modeling and Scaling Evaluation of Junction-Free Charge-Trapping NAND Flash Devices
Yi-Hsuan Hsiao, et al. (MXIC)
Simulation results show that the junction-free NAND Flash is scalable beyond the 15 nm node (half pitch) with reasonable DC characteristics, while the conventional “with-junction” NAND device shows much worse short-channel effect. The feasibility of a junction-free device on SOI for the future 3D NAND Flash is also examined.
- Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson’s Equation
Vita Pi-Ho Hu, et al. (National Chiao Tung University/Taiwan)
The results indicate that back-gate bias (Vbg) can mitigate the Read Static Noise Margin (RSNM) variability of ultra-thin body (UTB) SOI SRAM cells in the subthreshold region, and the improvement of SNM variability is more significant than the superthreshold region.
- High Mobility SiGe Shell-Si Core Omega Gate pFETS
Hemant Adhikari, et al. (SEMATECH, AMD, Texas A&M, Soitec, Intel)
Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.
- FinFET Resistance Mitigation through Design and Process Optimization
Cindy Wang, et al. (IBM, AMD)
The intrinsic FinFET device structure can provide an estimated 10-20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. The paper presents strategies for minimizing FinFET parasitic resistance, and discusses overall device design optimization.
- The Promise and Implementation of Three-Dimensional Integration (Invited)
Subramanian Iyer (IBM)
To address current limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way an SOC or ASIC is designed today. This talk examines the technology as it stands today and the challenges going forward, including the development of fine pitch vertical interconnects and the degrees of integration they would permit.