215th ECS Meeting

24-29 May 2009, San Francisco

For over a century, the Electrochemical Society (ECS) has been holding international meetings in the spring and fall of each year, providing a forum for exchanging information on the latest scientific and technical developments in the fields of electrochemical and solid-state science and technology. This spring, section E9 was devoted to SOI Device Technology.  It featured over 40 papers (#923-967). Abstracts for all of the E9 papers are available here. All papers can also be ordered from the ECS Digital Library. A short selection of highlights follows.

  • SOI Technology Driving the 21st Century Ubiquitous Electronics (#930 – Plenary talk)
    G. K. Celler (Soitec)
    A look at the growing role SOI plays as electronics expanding into all spheres of life, spreading far beyond computer systems, mobile telephony, and personal computers – into games, appliances, navigation systems, at-home health diagnostics, a variety of smart sensors at home, in cars and in the workplace. In the near future, electronic devices are likely to become integrated even in clothing.
  • Advanced FinFET Devices for sub-32nm Technology Nodes: Characteristics and Integration Challenges (#935)
    A. Veloso, et al. (IMEC)
    FinFET-based multi-gate (MuGFET) devices are one of the most promising candidates for enabling continued MOSFET scaling beyond the 32nm technology node, thanks to their improved Short Channel Effects (SCE) behavior and the possibility to control the channels potential without the use of heavy channel doping. This paper reviews and reports on the latest developments and technology challenges for these devices.
  • Ultra compact FDSOI transistors (including Strain and orientation) processing and performance (#936)
    C. Fenouillet-Beranger, et al. (STMicroelectronics, CEA-LETI, IMEP-INPG-Grenoble)
    This paper investigates the different ways to boost the FD-SOI device performance by using local strain approach and crystalline orientations.
  • Flexible Hybrid-Oriented Complementary Single-Crystal Si Thin-Film Transistors (#938)
    H. Pang, et al.  (U.Wisconsin-Madison, Soitec)
    Flexible, large area, lightweight and low cost electronics-macroelectronics are showing tremendous potential in various commercial and military applications.  This paper reports the first demonstration of flexible, single-crystal Si complementary thin-film transistors (TFTs) based on hybrid-oriented technology (HOT) on plastic substrate.
  • Advanced SOI and Ge-based Semiconductor-on-insulator Substrates Characterization (#939)
    A. Abbadie, et al. (Soitec)
    This paper details off-line characterization techniques and their challenges for new substrates based on Smart Cut™ technology that have emerged and could fulfill the requirements of future technology nodes, including Strained Silicon On Insulator (sSOI), strained SiGe on sSOI, and Ge On Insulator.
  • Advanced Design Methodology of High-Performance Sub-100-nm-Channel GAA MOSFET -Longitudinal Field Engineering (#943)
    S. Nakano, et al. (Kansai U., Atsugi TEC, Sony Corp.)
    Since the gate-all-around (GAA) SOI MOSFET has great potential due to its electrostatic confinement of carriers in the Si body, it is expected to yield advanced devices that offer high performance. This paper reconsiders the design methodology of the GAA SOI MOSFET and proposes an advanced concept to enhance its performance. The new idea is based on the acceleration of carrier velocity across the source junction, and is demonstrated by device simulations.
  • Low-Temperature Measurements on Germanium-on-Insulator pMOSFETs: Evaluation of the Background Doping Level (#947)
    W. Van Den Daele, et al. (IMEP-LAHC-INPG-Grenoble, CEA-LETI Minatec, Soitec)
    Fully-depleted GeOI structures are very attractive for excellent hole mobility and reduced leakage current. However, a critical issue is the positive VT shift for front and back channels, resulting in a parasitic off-state current in pMOSFETs. A strong positive back-gate voltage is needed to turn off the back channel and decouple front and back interfaces. This work explores, using systematic low-temperature measurements on various substrates, the doping problem as well as the subthreshold slope behavior, and discusses the origin of the VT shift.
  • SOI as Platform for Transition from Micro to Nano (#950)
    F. Balestra (Grenoble-INP)
    SOI-based devices seem to be the best candidates for the ultimate integration of Integrated Circuits on silicon for the end of the International Technology Roadmap for Semiconductors. This paper gives an overview of the main advantages of SOI for the Nanoelectronics of the next two decades.  Nanoscale CMOS and beyond-CMOS devices, based on innovative concepts, technologies and device architectures, are also addressed.
  • Floating-Body Memory: Concepts, Physics and Challenges (#960)
    M. Bawedin, et al. (U. Cambridge, IMEP-INPG-Grenoble, U. Catholique de Louvain)
    This paper discusses the last trends and challenges in terms of scaling, performance improvement and compatibility of floating-body memories in advanced technologies: from partially-depleted and fully-depleted SOI to double-gate devices.
  • 65nm Low Power (LP) SOI technology on HR substrate for WLAN and Mmwave SOCs (#961)
    C. Raynaud, et al. (STMicroelectronics, CEA-LETI)
    This paper presents a 65nm RF SOI CMOS technology, targeted as Low Power (LP) for mobile applications. 30% power saving compared to bulk with same 65nm design rules have been measured for the first time on High Resistivity (HR) 300mm SOI wafers. As HR SOI enables a great improvement of passives, this technology is a good candidate for future RF/Mmwave (@60GHz) SOCs.
  • Highly Reliable SRAM Circuit Technology Using FinFETs (#963)
    S. Ouchi, et al. (National Institute of AIST)
    A static random access memory (SRAM) is an important element as a working memory device integrated with logic circuits in system-on-a-chip (SoC). The device scaling has increased the memory capacity of SRAM in the limited chip die size, and its continuous extension is supposed in the future. However, the device scaling will cause a serious problem of variability in the device performance and thus a severe degradation in the SRAM cell stability, which affects the yield of LSIs. This paper presents a novel FinFET-based SRAM (named Flex-Pass-Gate SRAM), which enhances the noise margins in both the read and write operations.
  • Comparison of Short Channel Effect between SOI and sSOI Triple-gate MOSFETs (#966)
    K. Na, et al. (Kyungpook National U., IMEP-INPG-Grenoble, Uiduk U., Texas Instruments, Soitec)
    To compare short channel and coupling effects, triple-gate MOSFETs with the same geometrical factors were fabricated on SOI and sSOI substrates. The results showed that the sSOI devices exhibit poor SCE properties compared to SOI devices, such as rapid threshold voltage roll-off, large off-current leakage and strong coupling effect, which are believed to be mainly due to narrow bang-gap and low effective mass.
  • Opportunities and Challenges for Germanium and Silicon-Germanium Channel p-FETs. (#714)
    S.W. Bedell, et al. (IBM Research, Soitec, U. Tokyo)
    This work summarizes the results of Ge and high-Ge content SiGe channel p-FETS fabricated on lattice-engineered SGOI substrates with scaled high-κ  gate dielectrics and metal gate electrodes. It also presents the advantages of SiGe and Ge channels, such as better dielectric thickness scaling, carrier transport and threshold voltage VT control, as well as some of the disadvantages such as higher off-state leakage IOFF.

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