A Novel Device for Ultra-Low Power & More

Power is the biggest challenge to device scaling for digital applications. Aggressive MOSFET scaling gives rise to many critical challenges, which are typically addressed by scaling the supply voltage (VDD).

A transistor is switched on (current on: Ion) if the gate voltage (VG) is higher than the threshold voltage (VTH).  However, due to deleterious “short channel effects” (SCE) such as DIBL in deeply scaled MOSFETs, VTH typically has to be above 0.25V to escape the effects of subthreshold voltage swings.

This in turn sets a limit on the supply voltage (VDD), because you need to maintain an acceptable VDD/VTH ratio for good performance. For sub-45nm CMOS, the current level at which the transistor remains switched off (IOFF) becomes very high, and the ION/IOFF ratio reduces significantly.

The high IOFF point makes power dissipation, both dynamic and static (in standby mode for mobile devices, for example), an enormous challenge, especially for low power/low current applications.

The reduced ION/IOFF ratio is a particular problem for low stand-by power applications. When you measure and diagram the Ion/Ioff states, you want a very steep subthreshold slope, indicating that the change between on and off is quick, clear and dramatic, even at low power levels.

To overcome these problems, many good engineering solutions such as improving the device architecture, introducing materials into the channel region with superior transport properties and new gate dielectrics to reduce gate tunneling have been implemented. These techniques basically attempt to make small devices “long-channel” like.

We believe a better approach would be to exploit a new device configuration made feasible by the small dimensions and new materials.

Tunnel source SOI MOSFET

We have propsed a novel device concept, the Tunnel Source (PNPN) SOI n-MOSFET ([1]-[3]), based on the principle of band-to-band tunneling, as an alternative solution towards achieving devices with steep sub-threshold behavior. The device structure is shown in Figure 1.

Figure 1. The device structure of the novel PNPN SOI n-MOSFET.

The main feature of this fully-depleted (FD) SOI device is the concept of gate-controlled carrier injection through band-to-band tunneling at the source junction (see Figure 2).

At the International Conference on IC Design and Technology (ICICDT) in May, we presented further device simulation results, which confirm that our tunneling source SOI MOSFET is an attractive candidate for low power digital and analog operations. [4]

Figure 2. The principle of operation of the PNPN SOI n-MOSFET. • In (a), no band-to-band direct tunneling is possible even though the distance is small. The current level is small since the electrons from the p+ valence band can tunnel only to the trap states. • In (b), the tunneling width reduces and the channel conduction band goes below the p+ source valence band, providing states for the carriers to tunnel to. As a result, electrons from the p+ source valence band tunnel to empty states in the channel conduction band, creating device current. Tunneling resistance reduces as gate bias increases, and the device current is limited by drift field as in a conventional MOSFET.

The device can provide a very steep subthreshold slope (<60mv/dec at RT) and IOFF far beyond the limits of conventional devices.

The sharp swing facilitates a low IOFF, which is especially favorable for low standby and operating power applications. It does not change significantly, even at the high temperatures found in high-performance microprocessors.

The ION/IOFF ratio is improved by more than three orders of magnitude over conventional SOI.  Even with aggressive scaling, simulations indicate that the degradation in subthreshold swing and IOFF with scaling is negligible. This is particularly beneficial for low standby power and low operating power technologies.

Scaling the gate oxide thickness (TX) does not affect the source tunneling junction properties much and the dependence of ION on TOX is similar to that of a normal MOSFET. This implies that the device offers the advantage of relaxing the gate oxide scaling requirements, especially for subthreshold operation in low power applications.

Our simulation results also suggest that since SCEs are greatly suppressed, the PNPN device is extremely scalable and exhibits superior digital performance.

We conclude that the PNPN SOI n-MOSFET offers a viable solution to the challenge of stand-by and operating power reduction posed by aggressive device scaling, making it an attractive choice for ultra-scaled CMOS transistors. Furthermore, it can be realized in a vertical configuration for future 3-D integrated circuits.

[1] N. V. Girish, Ritesh Jhaveri and Jason C. S. Woo, “Tunnel Source MOSFET: A Novel High Performance Transistor”, IEEE 2004 Silicon Nanoelectronics Workshop, June 13-14, 2004, pp. 33-34.
[2] N. V. Girish, Ritesh Jhaveri and J. C. S. Woo, “Asymmetric Tunneling MOSFETs: A Novel Device Solution for Sub-100nm CMOS Technology”, International Journal of High Speed Electronics and Systems, vol. 16, no. 1, 2006, pp. 95-102.
[3] Venkatagirish N., Ritesh Jhaveri and Jason C. S. Woo, “The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor”, IEEE Transactions on Electron Devices, Vol. 55, No. 4, April 2008, pp. 1013-1019.
[4] Venkatagirish N., Ahmet Tura, Ritesh Jhaveri, Hsu-Yu Chang and Jason C. S. Woo, “The Tunnel Source MOSFET: A Novel Asymmetric Device Solution for Ultra-Low Power Applications”, to be published in 2009 IEEE International Conference on Intergrated Circuit Design and Technology, 2009.

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