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SOI: Simply Greener — The Campaign

This summer, the SOI Industry Consortium launched the “SOI Simply Greener” initiative, encouraging the electronics industry to adopt a broader application of SOI’s energy saving benefits.

Results from two studies offered by consortium members demonstrate both increased performance and reduced power consumption – the magnitude of the benefit applied to each is the designer’s choice.

  • A benchmark analysis was performed by ARM Holdings using a 24-stage interconnect-loaded datapath circuit.  When comparing IBM’s 45nm bulk high performance and 45nm SOI technologies, the SOI implementation resulted in a 25% circuit area reduction, 66% reduction in static power leakage and nearly 22% reduction in dynamic power with 5% higher performance.
  • A consumer product chip design that was migrated from 65nm bulk high performance to IBM’s 45nm SOI technology realized a 50% increase in operating frequency, more than 64% reduction in die area and a 38% reduction in power.

Whether designers put the emphasis on increasing or maintaining performance, significant power savings (as well as area savings) were realized with a move to SOI.

Get the Logo

The Consortium’s SOI: Simply Greener logo is freely available on the website. Members and supporters are encouraged to download it for use in their own presentations.

Industry Support

In support of the press announcement launching the initiative, the Consortium offered citations from industry leaders. A few follow here – you can read all of them on the SOI Consortium website.

“As we detailed in our recent report Semiconductor Technologies: The Potential to Revolutionize U.S. Energy Productivity, semiconductors already are the leading factor behind energy efficiency gains. SOI offers a major advance in the power efficiency of electronics, and with appropriate public policy, investment and usage these semiconductor technology gains can contribute to cumulative net electricity bill savings of $800 billion through 2030 for consumers and businesses in the United States alone, as well as creating an average of 500,000 new jobs per year and reducing energy-related CO2 emissions by more than 400 million metric tons annually over the period 2010 through 2030.”

John A. “Skip” Laitner, lead report author and Director, Economic and Social Analysis, American  Council for an Energy-Efficient Economy (ACEEE)

“UMC has been incorporating the benefits of SOI technology across multiple semiconductor applications such as MEMS, photonics, and our 65nm high-speed process portfolio. The energy efficiency of SOI adds to the attractiveness of the technology and conforms with UMC’s green initiative to provide environmentally friendly processes for our customers. We look forward to further developing SOI to provide customers with solutions that enable more innovative applications for a better and greener planet.”

W.Y. Chen, Senior Vice President, UMC

“The ‘SOI: Simply Greener’ initiative expresses the motivation and values that connect members of the SOI Consortium and foster collaboration around this energy-efficient technology. We welcome like-minded companies to join us in this meaningful work, to bring needed improvements to our industry and quality of life. The ecosystem is ready and accessible, and there is a broad space of opportunities for innovation in all areas: process; planar and 3D device architecture and optimization; digital, analog, RF, and MEMS design; EDA; IP development and optimization; heterogeneous planar and 3D integration; and services.”

Horacio Mendez, Executive Director, SOI Consortium.

“As a leader in low power design, Cadence continues to invest heavily in new technologies and methodologies to provide maximum power efficiency, now a key consideration for all designs. We are pleased to announce our end-to-end support for the SOI process within the Cadence Low Power Design Solution, thereby offering customers an integrated and low-risk path to maximizing the potential SOI benefits on their green designs.”

Dr. Chi-Ping Hsu, Senior Vice President, R&D Implementation Group, Cadence

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