Digital implementation with SOI: go with the float

Off-the-shelf solutions eliminate SOI design-time overhead.

Since the drive began to make SOI a more mainstream manufacturing process there has been concern over the cost. These considerations have overshadowed the benefits that the floating body of the SOI process brings, which includes better chip performance per watt, smaller die size, and better scalability at smaller geometries.

The concerns raised were not only regarding the cost of the manufacturing process itself — because any advance comes at a price — but also with the cost of actually implementing cell-based digital designs. The biggest concern: it would take many more man-hours of engineering time to make it through the digital design process as compared to bulk CMOS.

As it turns out, however, these challenges can be overcome by advancements in off-the-shelf design software if you just “go with the float.”

Figure 1

Keeps it simple

The single biggest hurdle for cell-based designers is the floating body effect that causes devices to switch at different speeds depending on their previous switching activity. Called the “history effect,” it can be dealt with in one of two ways:

  • it can be diminished by adding a body tie to the cell layout to fix the body voltage (adding another pin to the cells);
  • or, it can be left to float.

The first approach causes more routing congestion and makes timing closure more difficult. The second approach means you need to account for the floating body (a dynamic effect) during Static Timing and Noise Analysis (STA) (see Figure 1).

Going with the float has turned out to be the simpler solution as it solves the problem by simply tweaking the timing and noise library generation process and extending existing features of off-the-shelf STA software.

Transparent to the user

For instance, the Cadence® Encounter® Timing System leverages a hybrid flow for static timing analysis with min/max mode (see Figure 2) and very selective transistor-level simulation to account for the floating body during noise analysis. This change makes cell-based design with SOI technologies in tools such as the Cadence Encounter Digital Implementation System nearly transparent to the user, with a very nominal software runtime impact versus bulk CMOS (Figure 3).

Figure 2
Figure 3

With these advancements and refinements in design software along with the design kits provided by library developers, the floating body effects can be completely abstracted from the end user. There have already been many tapeouts using these industry-standard, off-the-shelf solutions that have enabled cell-based designers to build both ultra low-power and ultra high-performance designs in SOI technologies with virtually no design overhead when compared to bulk.

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