As the SOI circuit switches, the body voltages of the switching transistors will change from their previous steady state condition. This is called the history effect. This is one of the most interesting circuit design issues in SOI but it is also a benefit of SOI that contributes to the SOI performance advantage over bulk CMOS. Leveraging tools to model and predict the body voltage of the SOI transistors will lead to a successful SOI circuit design.
Typical SRAM design, however, uses a sense amp to sense the voltage of the bit cell. This requires matching transistors to properly sense the signal of the bit cell. Due to the history effect, these sensing transistors can have different body voltages and create a mismatch between them. In this case, the designer needs a solution to eliminate the history effect.
To address this type of design issue, SOI technology provides other types of transistors such as the body contact transistors. The body contact transistors have one additional terminal to provide the circuit designers the option of connecting the body to any nodes in their designs.
One common usage is to tie the body to ground (nfet) or Vdd (pfet) to reduce or eliminate the history effect. In this case, the SOI transistors behave similarly to bulk transistors.
The negative effects of the body contact transistors are that they are larger than the non-body contacted devices so the layout will need to be optimized to fit within the pitch of the bit cell.
To eliminate the mismatch in the SRAM sense amplifier, the body contact transistors are used on the sensing transistors of the SOI SRAM sense amplifier design (Figure 1).