Conquering Convergence

ST looks at a hybrid FD-SOI/bulk approach to SOCs for multimedia.

The heterogeneous nature of System-on-Chip (SOC) design for the next generations of wireless, high-performance, low-power multimedia applications makes it a complex balancing act. Our research indicates that a hybrid FD-SOI/Bulk, high-k/metal-gate platform is an excellent candidate for such applications, most probably around the 22nm node.

We have now demonstrated the successful integration of intellectual property (IP) for hybrid FD-SOI devices at 32nm using SOI wafers with extra-thin (ET) top silicon and ultra-thin (UT) box.

On the threshold

Modern multimedia SOCs support a plethora of uses. Some will benefit primarily from low operating power (LOP); others from low standby power (LSTP); and yet others from high-performance (HP). At the transistor level, the threshold voltage (Vt) favors one of these characteristics. Designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.

We have demonstrated the ability of FD-SOI technology to handle multiple Vt devices and I/Os through a cost effective scheme.

For a start, an FD-SOI strategy keeps the channel undoped, eliminates excessive Short Channel Effect (SCE) and enables Vt and sub-threshold slope values suitable for LOP operation.

Designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.

That’s good for LOP.  However, for LSTP, you need to decrease Ioff – which requires high Vt. We solved this by adding a ground plane (GP) under the thin BOX.

But for the analog and high-performance pieces of the puzzle, you need lower Vt values, which we achieved by adding back biasing to the UTBOX/GP combination.

Speed up

When considering speed in the context of LOP, the Ion parameter used in the high-performance world is not effective. We’ve found that a better criterion is effective current (Ieff). In the electrostatics of FD-SOI devices, Ieff is improved because of better DIBL: Drain Induced Barrier Lowering.

To get the right DIBL, you need to choose the right substrate solution.  We have found that an ultra-thin BOX enables us to approach the electrostatics of Double Gate devices, while retaining the simplicity of a Single Gate scheme. We have demonstrated that FD-SOI, with our UTBOX flavor, enables very significant DIBL reduction from which we expect a boost in device speed of up to 20%.

Hybrid integration

With all of the IP needed for an SOC, there are a few pieces that still rely on a bulk substrate. Our approach is a hybrid co-integration.  Where we need a bulk device, we etch away the top silicon and thin BOX to reveal the bottom silicon layer of the SOI substrate. The resulting “step” created between the FD-SOI and bulk is so small (<400Å) that it’s not a problem for subsequent lithography processes (see figure).

In conclusion, continued efforts are needed to fully exploit the excellent potential of FD-SOI for 22nm and below. The hybrid co-integration approach enables a focus on the right priorities and guarantees availability of an efficient solution for all types of IP. Therefore, hybrid FD-SOI is very promising for low power multimedia SOC applications.

TEM cross of the hybrid FDSOI/bulk co-integration in an SRAM cut periphery. The BOX thickness is 25nm. (Courtesy: STMicroelectronics)

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