ETSOI Substrates: What We Needi

IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why.

ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction leakage and GILD, which are critical to low power platforms.
Electrostatics for ETSOI devices on the other hand, are controlled by the thin silicon on insulator (SOI) channel. One critical challenge is that threshold voltage variation for ETSOI is largely determined by silicon thickness variations. While ETSOI offers the promise of improved device characteristics, when billions or more of these transistors are integrated to create large scale circuits, the circuit performance will depend to a large extent on the flatness of the starting SOI wafer.

There are two regimes of thickness variation at issue: local variations and global variations.

Local variations affect the matching of nearby transistors and are typically reflected in a parameter called AVt. Measurements performed on SRAM FETs yield record low AVt values[1], suggesting ETSOI SRAM operating voltages can be lower compared to conventional technologies and also that local silicon thickness is very well controlled.

Global threshold voltage (Vt) variations affect the consistency of performance and power consumption across a die and from die to die. Careful measurements reveal that threshold voltage Vt variation is 25mV for every 1 nm of Si thickness variation[2].

At the beginning of the ETSOI project, we used PDSOI wafers thinned down to our target thickness of 6nm. Since PDSOI electrostatics are not controlled by TSi, the specification for silicon variation is relaxed compared to what is ultimately needed for ETSOI technology. We then requested extremely flat and uniform starting material from Soitec and are currently receiving wafers with a TSi specification of 12nm +/-0.5nm.
The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. To reach full industrialization, we need a high-volume supply of wafers with thickness variation of less than +/-0.5nm with corresponding wafer-to-wafer uniformity.

We have set targets for our suppliers to reach full substrate maturity, both in terms of local and global variations, in line with ETSOI technology needs.

ETSOI Device Technology Features• Small device dimensions fit 22nm pitch. Lgate ~25nm, TSi ~6nm, spacer ~15nm, High-k/MG • Faceted raised source-drain (RSD) to reduce parasitic capacitance • Implant-free S/D and extension to reduce series resistance

Meeting the challenges

At IBM, we have solved many of the major manufacturing challenges for ETSOI.

High external resistance and parasitic capacitance have been alleviated by using in-situ doped and facetted raised-source drains. Si consumption has been minimized by optimizing gate and spacer etch processes.  Substrate cost has been mitigated by process simplification and channel thickness variation has been minimized by using extremely flat wafers.

IBM has also demonstrated transistors with TSOI as thin as 3.5nm, which could meet the requirements of the 11nm node, although control of the Tsi variations would be even more demanding[3].

In conclusion, we see ET-SOI as a viable low-power (LP) technology for the 20nm LP node and beyond.  It offers:

  • Low leakage, good electrostatics,
  • Low cost by virtue of simplified processing, and
  • Extendibility to multiple generations.

Substrate uniformity is critical. We believe substrates are approaching technology readiness, as demonstrated by experimental measurements of local and global Vt variations.

Leave a Reply

Your email address will not be published. Required fields are marked *