EuroSOI 2010

25-27 January 2010, Grenoble, France

EuroSOI is an annual, international forum to promote interaction and exchanges between research groups and industrial partners involved in SOI activities all over the world. This year’s conference was held at Grenoble’s Minatec innovation campus, an international center for micro and nanotechnologies. An intimate but lively event, the conference welcomed about 120 top researchers, and featured over 60 papers.
The tutorials included “SOI technologies and circuits,” presented by J. Hoentschel of GlobalFoundries, and “SOI substrate for RF?” by Eric Desbonnet of Soitec.
A selection of papers follow here.

SOI- the next five years: The critical role that SOI will play in the semiconductor ecosystem and how it will happen

H. Mendez, SOI Consortium (Invited).
The talk described the critical role that SOI will play in the next several generations, especially at 20nm, whre the confluence of these challenges will dictate a departure from the traditional forms of scaling.

Digital Frequency Locked Loop for Low Power Operation in Complex Multi-Core Systems

Christophe Tretz, et al. (IBM)
The authors propose an all-digital clock generator concept ideal for low-power operations and immune to hysteresis.

Power Switch Optimization in 65nm PDSOI Considering Physical Implementation Constraints

Julien Le-Coz, et al. (STMicroelectronics, CEA/Leti)
Several PD-SOI power switch candidates were compared in an implementation-constrained environment. The authors conclude that the best solution is a BC transistor, with a higher than minimal gate length. This enables standby leakage currents that are not higher than in bulk.

High voltage MOS transistors on 0.18μm SOI CMOS technology

G. Toulon, et al. (LAAS, U. Toulouse, Atmel)
The paper analyzes the voltage capability of lateral power N and P-channel MOS transistors manufactured on a 0.18um SOI CMOS technology by means of TCAD simulations to explain the electrical results of the measured structures.

Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach

J. S. Su, et al., (National Taiwan University and UMC)
The authors conclude that current behavior is due to the floating-body-effect-induced parasitic bipolar device.

Partially Depleted Double-Gate 1T-DRAM Cell Using Nonvolatile Memory Function for Improved Performance

K. -H. Park, et al. (IMEP, Uiduk U. at Gyeongju, Seoul National U.)
The authors propose a new, double-gate 1T-DRAM cell combining a SONOS-type storage node on the back-gate (control gate) for nonvolatile memory. The concept was experimentally validated with 0.6um gate length devices fabricated on SOI wafers.

Capacitor-less A-RAM memory cell:Operation, scaling and expected performance

Noel Rodríguez, et al. (U. Granada, IMEP-LAHC/MINATEC)
The authors detail the physical operation of A-RAM capacitator-less, single transistor memory cell, featuring non-destructive reading and very simple and practical waveforms for word and bit lines. They go on to explore its possibilities for embedded memory applications in terms of scalability and retention time.

Strained-SiGe p-MOSFET with LaLuO3 as high-k gate dielectric and TiN as metal gate

W.Yu, et al. (Forschungszentrum Jülich, Shanghai Institute of Microsystem and Information Technology, CAS, CEA-Leti, Soitec)
A compressive strained SiGe channel p-MOSFET with LaLuO3 as gate dielectric and TiN as metal gate was fabricated and characterized. The mobility extracted from split C-V measurements is comparable to values reported for other high-k materials on SiGe.

High Mobility CMOS: First Demonstration of Planar GeOI pFETs and SOI nFETs

C. Le Royer, et al. (Leti, with the IBM-ST-Leti Alliance)
For the first time, the coefficient n, linking the inversion charge and the effective field, has been extracted and validated for holes in Ge-on-Si and FD GeOI pMOSFETs. A difference of 20% has been found between the two structures, which has a serious impact on effective mobility analysis for advanced GeOI-based pMOSFETs.

RF acoustic resonators with single crystal piezoelectric thin films transferred by the Smart Cut™ technology

M. Pijolat, et al.(CEA-Leti, Soitec, Femto ST).
For the next generation of ultra-wide band RF filters, the authors propose a potential technology based on Smart Cut(tm) technology, applied to a single crystal piezoelectric thin layer. They successfully transferred and confirmed the integrity of single crystal lithium niobate thin layers.

Germanium Integration on Silicon for High Performance FETs and Optical Interconnects

K. Saraswat (Invited) (Stanford U.)
The author reviews recent results on heterogeneous integration of Ge devices on Si,
as well as the first application of Ge for high-performance MOSFETs. He concludes that successful integration of Ge on Si should allow continued scaling of Si CMOS to below the 22nm node.

Synthesis and characterization of crystalline silicon ribbons on insulator using catalytic Vapor-Liquid-Solid growth inside a cavity

Aurélie Lecestre, et al. (IEMN, STMicroelectronics, CEA-LITEN, Laboratoire de Photonique et de Nanostructures, Ecole des Mines)
The authors demonstrated that guided and confined Vapor-Liquid-Solid (VLS) growth can be used to produce single crystalline thin, SOI-like silicon ribbons on an amorphous substrate at temperatures as low as 500oC. For the first time, their crystalline nature was revealed based on Electron Backscattered Diffraction (EBSD) characterization. The analysis places the proposed synthesis techniques in favorable position to develop a high-performance TFT technology.

Leave a Reply

Your email address will not be published. Required fields are marked *