Researchers in academia have partnered with industry to increase understanding of critical issues in advanced non-classical CMOS devices.
Highly scaled devices present a new range of challenges with respect to critical issues such as leakage current, short-channel effects, high-field effects, variability, reliability, noise and parasitic impact. Device structure and material innovation are the primary enablers for performance enhancement in CMOS technology.
The gate-all-around (GAA) silicon nanowire transistor (SNWT) is a kind of multiple-gate SOI transistor that is considered as one of the promising candidates for ultimate scaling, due to its excellent electrostatic control capability, improved transport properties and feasible device design.
As shown in Figure 1, this kind of device has a very unique structure: the gate material surrounds the channel region – the silicon nanowire – on all sides. This three-dimensional surrounding gate-stack has multiple crystallographic interface orientations, and there is a sharp transition from the large source/drain region to the narrow nanowire part (of the source/drain extension).
Because of the extreme length-to-width ratio, the nanowire channel can be considered as “quasi-one-dimensional”, which confers properties not seen in 3D materials.
Some of the critical issues may be even more complicated, giving rise to new challenges in device engineering of SNWTs.
In previous work, our team has investigated the parasitic effects, reliability and noise characteristics of SNWTs. In a recent paper we presented at the IEEE SOI Conference, we discussed the self-heating effect (SHE) and variability in SNWTs, which are two key issues of nano-scaled devices for practical circuit applications.
Figure 2 shows the SEM image of the fabricated SNWT with 10 nm diameter.
As devices size scales and circuit density increases, the self-heating effect becomes a critical concern for device performance and reliability degradation. Due to the 1-D nature of nanowire and increased phonon-boundary scattering in the GAA structure, the self-heating of SNWTs in bulk is comparable or even a little bit worse than SOI devices.
The ultimate performance of SNWT-based circuits may be intrinsically limited by SHE. Therefore, special design approaches are needed, such as new thermal-aware design methodology for SNWT circuits.
Variability in SNWTs
Highly-scaled CMOS devices and circuits suffer from serious variability issues. For SNWTs, with their ultra-scaled dimensions of the nanowire and surrounding gate stack structure, variability shows unique features. Identifying and understanding these specificities can help provide guidelines for robust SNWT design. The variation sources in SNWTs are schematically shown in Figure 3.
Our experiments found the SNWT-based SRAM cell more stable than its planar counterparts, due to the superior electrostatic control and thus better immunity of surface potential variations. That makes SNWTs a good candidate for future SRAM cell applications from the perspective of variation suppression.
Like in any design, there are tradeoffs to be made when designing nanowire diameters. The use of an SOI substrate for simplifying the nanowire device fabrication may be a better approach. In any case, there is a long road ahead, as we need to further our in-depth physical understanding of the device. However, the GAA SNWT’s excellent electrostatics, improved transport and easier 3D integration should ultimately enable new applications – in both the “More Moore” and “More Than Moore” realms.
The author wishes to acknowledge the work of her students and the staff at the Peking University cleanroom, and the collaboration of Dr. D.-W. Kim and Dr. D. Park of Samsung.
 J. Zhuge et al., T-ED, p.2142, 2008
 R. Wang et al., IEDM, p.821, 2007; L. Zhang et al., IEDM, p.123, 2008
 J. Zhuge et al., EDL, p.57, 2009; R. Wang et al., IEDM, p.753, 2008
 Self-Heating Effect and Characteristic Variability of Gate-All-Around Silicon Nanowire Transistors for Highly-Scaled CMOS Technology (invited). 2010 IEEE SOI Conference.