“SOI SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA),” says ARM SOI guru Jean Luc Pelloie.
With that in mind, the ARM team presented a quiet paper at the last IEEE SOI Conference (Oct. 2010) – but one that has important implications for the industry. “Timing Verification of a 45nm SOI Standard Cell Library” is not yet available on the IEEEXplore site, but Jean Luc summarized the key points for Advanced Substrate News (ASN) (see http://www.soiconsortium.eu/2010/12/right-timing/).
The take-away message: “It’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.”
The history effect is just another “corner”. Since it’s accurately accounted for in the physical IP libraries, it’s pretty much transparent in the design flow, he explains.
On the foundry side, says Jean Luc, ARM is helping leading foundries retune their 45nm SOI SPICE models for greater accuracy.
If you’re a designer, is the history effect something that still concerns you? Does this news make you feel a little more sanguine about diving in to SOI? Leave a comment and let us know.
(BTW, ARM’s been a regular contributor to ASN – see http://www.soiconsortium.eu/pages/companies/arm/ for more.)