Up to 80% additional performance improvement on an ARM Cortex M0. 40% lower power for SRAMs. These are the amazing planar FD-SOI results just announced by the SOI Consortium. Things are suddenly looking much brighter in the world of low-power, high-performance chips for mobile and consumer apps.
An A-list of companies collaborated on this assessment/characterization – ARM, GlobalFoundries, IBM, ST, Soitec and Leti – so you know the results are really solid. People want PC performance in a cell phone (without having to recharge the battery three times a day, thank you!). These guys know what it takes to make the chips that can make it happen.
For designers and manufacturers, FD-SOI is a win-win: design flow is the same as bulk, so there’s no learning curve; manufacturing is vastly simplified, so it costs less.
Let’s make a few things clear here: that +80% – that’s on top of the +25% improvement you’d get moving from one node to the next. So if you move to FD-SOI at the same time you’re moving down a node, you can get (do the math) a +125% (!!) improvement in performance – and lower power. Designers sweat blood for a few percentage points of performance improvement, and here you get more than double – and it’s cheaper and easier. Wow.
The 40% power savings on the SRAM (which now typically accounts for over half the chip) – that’s because with FD-SOI you can run it reliably at lower voltages – which of course saves battery life.
It’s worth pointing out that much of this success is due to some amazing work by Soitec. Their R&D folks first wrote about the ultra-thin wafers needed for FD-SOI in ASN five years ago. They’ve been working on perfecting those wafers ever since – and supplying them to the IDMs and foundries for some time now, so those guys could get on with their early legwork. The requirements for silicon and BOX layer thinness and smoothness are draconian: we’re deep in the world of Angstroms here.
All the while, there were some hefty naysayers claiming the wafer requirements could never be met. But guess what: those requirements have been met – and the wafers are ready to roll.
I urge you to read Christophe Maleville’s article in our most recent edition: Wafers for Fully-Depleted Devices: Ready for Volume – and look at the all the checkmarks on that list of requirements. It’s really some impressive work.
So, want to know more FD-SOI? Let me point you at some sources:
- The SOI Consortium – they’ve been running FD-SOI workshops and design clinics for over year, and all the presentations are available on their website. Especially, check out the white papers on FD-SOI design impact and the Q&A.
- In ASN#15, we devoted an entire feature to FD-SOI, with contributions from ST, IBM, Hitachi, Leti, Soitec and more.
- A quick layman’s guide to the differences between partially- and fully-depleted SOI. I wrote this three years ago, so the “challenges” have all been met by now, but the basic concepts are all here.
- Enter FD-SOI in the ASN search engine at the top of this page.
- Click on the FD-SOI “tag” here on the right side of this ASN page.
- A lot of the big break-throughs were first announced at the IEDM in 08 – Leti/ST/Soitec and Hitachi shared details with us in ASN#12.
Planar FD-SOI: it’s the start of something big.