ESD Protection for Advanced SOI

Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise.

Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. The I/O data-rate increasingly limits the capacitive budget, exacerbating the shrinkage of ESD design space.

It is important to find ESD solutions that minimize parasitic loading while achieving superior robustness.

Silicon-on-insulator (SOI) technology presents some distinctive challenges to ESD design. The buried oxide (BOX) layer makes vertical and deep body ESD structures infeasible. The lateral SOI diode based (“rail-based”) protection approach is becoming less effective in the high-current Charged Device Model (CDM) domain, owing to excessive voltage build-up along the ESD path involving power buses, power-clamps (Pclamp), and diodes.

Figure 1: Pad-based local clamping scheme. Red arrows represent the pad-to-Vss ESD current path, which does not include the upper diode or the power buses (crossed-out). The double-triangle symbol represents a local clamping device, such as the double well field effect diode (DWFED).

The pad-based “local clamping” scheme (Figure 1) is a promising option. By connecting an ESD device directly between the pad and Vss, it allows the ESD current to flow from the pad to ground without going through the resistive path (shown as crossed out in Figure 1) and the Pclamp. This way, the pad voltage is considerably reduced, immediately expanding the design space.

New devices

For local clamping ESD devices, it is vital to engineer their turn-on voltage in order to avoid accidental turn-on during normal operation and to minimize leakage current. Low capacitance and resistance are also required. Furthermore, an important CDM specific requirement is that the device should turn on faster than the CDM event to start shunting current before charge accumulation raises the pad voltage.

To meet these requirements, devices such as the double well field effect diode (DWFED) and FED have been developed. Figure 2 shows the example structure of DWFED and the triggering mechanism. During normal operations, the inverter pulls the DWFED’s gate voltage to low, helping to preserve the DWFED’s intrinsic PNPN state.

Figure 2: (a): The DWFED structure. (b): Behavior during normal operations. Device in “PNPN” mode, minimizing the leakage current. (c): Triggering behavior during ESD. Device in “PN” mode, shunting large ESD current.

This is similar to a silicon-controlled rectifier’s (SCR) OFF mode. In an ESD event, the Vdd is pulled low by the de-coupling capacitance and the power clamp between Vdd and ground, turning on the PMOS in the inverter. The DWFED gate is now pulled high, creating an inversion layer in the P-well (for positive ESD at the pad). This inversion layer connects the NW and N+ regions, collapsing the junctions in between. The device converts to a P-N diode ON mode between P+ and NW.

Deeply Scaled PD, FD-SOI and FinFETs

In our recent work, various types of field effect devices have been experimentally shown in PD-SOI to be suitable for local clamping. Both FED and DWFED exhibit capacitance below 0.35 fF/μm, which is a significant improvement over the SCR. Their turn-on speed under CDM is controlled to below 0.5 ns.

The device design has been guided by Technology CAD (TCAD) modeling. Design tradeoffs are evaluated with different well dopings to highlight the important parameters. The field effect devices are likely to be advantageous in ESD applications in ultra thin body SOI (also known as planar FD-SOI) and FinFET due to their reduced sensitivity to the scaling of silicon film dimensions.



S. Cao, A. A. Salman, J.-H. Chun, S. G. Beebe, M. M. Pelella and R. W. Dutton, “Design and Characterization of ESD Protection Devices for High Speed I/O in Advanced SOI Technology,” IEEE Transactions on Electron Devices (TED), vol. 57, no. 3, pp. 644-653, March 2010.

S. Cao, J.-H. Chun, S. G. Beebe and R. W. Dutton, “ESD Design Strategies for High-speed Digital and RF Circuits in Deeply-scaled Silicon Technologies,” IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 57, no. 9, pp. 2301-2311, Sept. 2010.

A. Salman, S. Beebe, M. Pelella, and G. Gilfeather, “SOI lateral diode optimization for ESD protection in 130 nm and 90 nm technologies,” in Proceedings of International EOS/ESD Symposium, 2005, pp. 421–427.

S. Cao, J.-H. Chun, A. A. Salman, S. G. Beebe, and R. W. Dutton, “Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology,” Microelectronics Reliability, vol. 51, no. 4, pp. 756-764, April 2011.

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