What are you going to do with your SOCs at 20/22nm? The options seem to boil down to just staying on bulk CMOS, or changing to FinFETs or planar, fully-depleted (FD) SOI-based CMOS.
Though some may find comfort in staying on bulk CMOS, it’s getting very complicated – and complicated get expensive fast. The FinFET option (which can be on bulk or SOI) is exciting for the longer term,but in the short term still raises significant design and manufacturing challenges. That leaves FD-SOI — which in terms of cost, performance, power and complexity is turning out to be an extremely attractive option.
You’ve probably heard that FD-SOI promises major savings in power (40%) and/or a big boost in performance (25 to 80% – depending on the Vdd and design type – over low-power bulk technology). And a recent study found that FD-SOI will be cheaper to fab than bulk because it’s less complicated.
Perhaps also you’ve heard that designing for FD-SOI is pretty much the same as designing for planar bulk CMOS. But what would it mean from a design perspective to actually port your existing bulk SOCs to FD-SOI? What would the impact be? What would you have to do?
Member companies of the SOI Consortium – including ARM, Leti, UCL, IBM, GlobalFoundries and Soitec – have tackled these questions. The Consortium just posted a major technical white paper called, “Considerations for Bulk CMOS to FD-SOI Design Porting”.
It’s a must-read for anyone working on the leading edge.
Over the next few months, here at ASN we’ll be publishing excerpts and summaries. But to give you an idea of the magnitude of this paper, here is an overview.
The scope of the study is to examine the efforts required to port existing bulk CMOS designs to FD-SOI at the same node – so we’re comparing apples to apples, as it were. It considers both bulk-to-FD-SOI IP Porting and full chip design porting.
With respect to the full chip design porting, it considers two potential paths:
- the straightest possible porting from bulk to FD-SOI – ideally, no change in place-and-route, and as close as possible to keeping the same GDS with all FD-SOI-specific updates automatically handled at mask generation;
- or, optimizing the SOC implementation to take full advantage of FD-SOI options like back-biasing.
There’s a section on the FD-SOI design specificities that need to be taken into account. It sorts out in significant detail devices and electrical characteristics that are addressed at the technology level, looks at any impacts at the designer level, and indicates what is foundry-dependent.
The meat of the document is in a section called “Impact Per Design Domain”. Here it goes into the impact of an FD-SOI port on logic library cells, memory compilers, I/Os and ESD protections, analog & mixed-signal IP, and the choice of porting approach (fastest vs. most optimized) right down to sign-off considerations.
Those considering the “most optimized” approach will want to look at the appendices that go into great detail on back-biasing for VT shifting or tuning (more efficient than, although similar to the body-biasing used in some bulk designs), as well as “native” multi-VT.
Finally, the References section is a treasure trove, listing the most important FD-SOI papers presented at the top conferences over the past few years – including VLSI, IEDM, ISSCC, the SOI Conference and more.
Overall, the approach is technical but approachable. Let us know what you think.