SOI Conference Shows SOI Driving Key Roadmaps

2011 IEEE SOI Conference

The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at the heart of many a roadmap.

Consider some of the plenary talks.

First was Competitive SOC on UTBB SOI by Thomas Skotnicki of ST Microelectronics.  This was a detailed presentation on ST’s vision for planar fully depleted (FD) SOI (which he described as equivalent to a FinFET rotated by 90 degrees). Here are some of  the key points:

  • ST’s FD objectives are +30% performance at Vdd 1V and +40% at Vdd – 0.1
  • The FD Process saves 10% cost over the equivalent bulk process, mainly because 25 implantations steps are suppressed.
  • The process options for 28, 20, and 14nm were detailed.
Jean Luc Pelloie, Director of SOI Technology, ARM, presenting at the 2011 IEEE SOI Conference.
Jean Luc Pelloie, Director of SOI Technology, ARM, presenting at the 2011 IEEE SOI Conference.

Next up was FDSOI Design Portability from BULK at 20nm Node by Jean Luc Pelloie of ARM. Jean Luc, who is ARM’s Director of SOI Technology, described how a Cortex M0 implementation flow was proven in 22nm SOI. He emphasized that the design migration to FDSOI is straightforward in terms of EDA flow: the interconnects routing, parasitics are identical, and FDSOI transistors’ electrical behavior is similar to bulk transistors.

There’s no floating-body effect, no history effect, no timing variability, he reminded attendees. Logic and memories are identical. That said, further optimization can be done to account for different electrical features at the device level. The few differences specific to FDSOI are not design related but more process/device related (SPICE models, antenna effect, ESD protection, potential parasitic bipolar, and back-gate bias).

Look at the results ARM’s seeing:

Cortex-M0 benchmark – performance comparison between 28nm bulk and 20nm FDSOI
Cortex-M0 benchmark – performance comparison between 28nm bulk and 20nm FDSOI. (Courtesy: ARM, 2011 IEEE SOI Conference)

As SOI Consortium Director Horacio Mendez pointed out in ASN this summer, you typically expect to get about a 25% improvement in performance moving to the next node. But ARM’s showing that if you move to the next node and move to FD-SOI, you get really phenomenal results, especially at the lower supply voltages.

In the Hot Topics Session, Bruce Doris (IBM) announced new High Performance values for FDSOI in his presentation on The Future of SOI Transistor Technology:

  • At Vdd 1V, for Ioff 100nA, he reported NFET Ieff 0.82 and Isat 1.4 mA/um
  • At Vdd 1V, for Ioff 100nA, he reported PFET Ieff 0.68 and Isat 1.2 mA/um

Integration of photonics and electronic circuits on SOI was the subject of both Yuri Vlasov’s (IBM) plenary talk, and Juthika Basak’s (Intel) Short Course.

Papers from Peregrine and Soitec showed some impressive results for their new mass-produced bonded silicon-on-sapphire (BSOS) wafers for RF applications. In Strain Reduction in Silicon-on-Sapphire by Wafer Bonding BSOS films showed 56% higher electron mobility than traditional SOS; and RF switch performance in BSOS was better than GaAs PHEMTs.

J.P. Raskin (UCL), who’s doing some fascinating work, presented Sensing and MEMS Devices in Thin Film SOI MOS Technology.

And finally, a team from MIT/Lincoln Labs once again slipped in a tantalizing concept in their late paper submission entitled SOI Circuits Powered by Embedded Solar Cell.

Here’s a link to the program. I’ll cover more of the papers presented at this conference in upcoming PaperLinks articles.  But clearly, the 2011 IEEE SOI conference was an excellent one.

Many thanks to Nicolas Daval and Christophe Didier of Soitec for their help on this blog entry.

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