Members of the SOI Consortium have released a major white paper addressing the porting of SOC designs from bulk to FD-SOI.
SOC designers face a critical juncture at 20/22nm. Choices must be made whether to stay on bulk CMOS, change to a FinFET architecture, or move to planar, fully-depleted (FD) SOI-based CMOS.
Power management and variability control are making scaling in bulk CMOS much more complex. The FinFET option, on the other hand (which can be on bulk or SOI) raises significant development and manufacturing challenges in the short term (although these will probably be less of an issue as time goes on). The planar FD-SOI option, however, is very attractive both for the short and longer terms with respect to cost, performance, power and complexity, especially for low-power, high-performance challenges.
FD-SOI has been shown to enable major savings in power (40%) and/or a significant increase in performance (25 to 80% – depending on the Vdd and design type) over low-power bulk technology. A recent study by IC Knowledge found that FD-SOI will be more cost-effective than standard bulk CMOS largely thanks to the fact that it requires significantly fewer processing steps.
However, the SOC designer may well ask how FD-SOI would impact the design flow.
Member companies of the SOI Consortium – including ARM, Leti, UCL, IBM, GlobalFoundries and Soitec – have now addressed the concerns of designers by issuing a major technical white paper entitled, “Considerations for Bulk CMOS to FD-SOI Design Porting”.
It is available immediately as a free download from the SOI Consortium website.
Scope of the paper
The scope of the study is to examine the efforts required to port existing bulk CMOS designs to FD-SOI at the same node. It considers both bulk-to-FD-SOI IP Porting and full chip design porting.
With respect to the full chip design porting, it considers two potential paths:
- the straightest possible porting from bulk to FD-SOI – ideally, no change in place-and-route, and as close as possible to keeping the same GDS with all FD-SOI-specific updates automatically handled at mask generation;
- or, optimizing the SOC implementation to take full advantage of FD-SOI options like backbiasing.
A section on FD-SOI design specificities considers in significant detail devices and electrical characteristics that are addressed at the technology level. It also examines any impacts at the designer level, and indicates what is foundry-dependent.
The heart of the document is a section called “Impact Per Design Domain”. This addresses the impact of an FD-SOI port on logic library cells, memory compilers, I/Os and ESD protections, analog & mixed-signal IP, and the choice of porting approach (fastest vs. most optimized) all the way down to sign-o considerations.
For designers considering the “most optimized” approach, the appendices go into great detail on back-biasing for VT shifting or tuning (which is more efficient than, although similar to the body-biasing used in some bulk designs), as well as “native” multi-VT.
Finally, the References section is an excellent resource, listing the most important FD-SOI papers presented at major conferences over the past few years – including VLSI, IEDM, ISSCC, the SOI Conference and more.
The goal of this white paper is to really address the issues at a technical level. However, it should also be useful to executive decision makers. We welcome your feedback. You will also find that there are dozens of technical presentations available on the SOI Consortium website addressing specific topics. Please feel free to contact the Consortium for more information or if you’d like to engage in more in-depth discussions regarding the upcoming choices we all face.