Held every December, the IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org) presents the best applied research in electronics from corporate, university and government labs around the world. Brief descriptions of the IEDM 2011 papers with research related to SOI and some other advanced substrates follows. The full program is available at: http://www.his.com/~iedm/program/11advprg.pdf The papers themselves are now available through the IEEE Xplore Digital Libary. Links are embedded in the titles here.
Session 4, Paper 1
Architecting Advanced Technologies for 14nm and Beyond with 3D FinFET Transistors for the Future SoC Applications (Invited)
A. Keshavarzi, D. Somasekhar, M. Rashed, S. Ahmed, K. Maitra, R. Miller, A. Knorr, Jin Cho, R. Augur, S. Banna, C-H. Shaw, A. Halliyal,U. Schroeder, A. Wei, J. Egley, K. Korablev, S. Luning, M-R. Lin, S. Venkatesan, S. Kengeri, G. Bartlett (GlobalFoundries).
This paper focuses on circuit and device interactions for architecting the advanced technologies for 14nm and beyond using 3D fully depleted FinFET transistors for the future SoC applications, citing various challenges & potential solutions. It notes that FinFETs can be fabricated on bulk or SOI wafers, however there is trade-off of ease of isolation, less RDF, Fin height control, and lower Cj vs wafer cost. While Bulk FinFETs provide more strain engineering capability, the authors note that strained SOI substrate showed elevated mobility due to induced uniaxial strain. (They cite a June ’11 paper entitled Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High-k/Metal-Gate nFinFETs for High-Performance Logic Applications (IEEE Electron Device Letters, K. Maitra et al) which found that Strained SOI (SSOI) FinFETs exhibit drive currents suitable for high-performance logic technology, and that there is a ~ 15% mobility-induced ION enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths.) They also note that that FinFETs will have good SER performance for better system reliability due to the device being segmented and even more isolated when deployed on SOI substrate.
Session 5, Paper 4
Xingsheng Wang, Andrew R. Brown1, Binjie Cheng and Asen Asenov (University of Glasgow)
The comprehensive full-scale simulation study of statistical variability and reliability in the emerging and scaled 3D FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. All major sources of statistical variability are investigated, along with interface trapped charges associated with N/PBTI.
Session 5, Paper 6
J.J.-Y. Kuo, P. Su (National Chiao Tung U)
A self-heating induced feedback (SHFE) effect on the drain current mismatch has been reported and modeled. The accuracy of the new model has been verified with experimental data. This effect needs to be considered when one-to-one comparisons between SOI and bulk devices regarding the variability are made. By 3-D atomistic electro-thermal simulations. The authors show that the SOI FinFET device exhibits smaller drain current variation than the bulk FinFET counterpart due to the SHFE.
Session 5, Paper 7
Terence B. Hook*, Maud VinetO, Richard Murphy*, Shom Ponoth* Laurent GrenouilletO (*IBM Microelectronics, OLETI)
This paper examines transistor threshold voltage matching as a function of silicon thickness variation in ETSOI (Extremely Thin Silicon On Insulator) transistors. By analyzing AFM data, threshold voltage, and electrical silicon thickness data the authors show the behavior is not random, but has a strong dependence on distance, a weak dependence on area, and is amenable to improvement through process optimization. Adjacent transistors are very closely matched
Session 7, Paper 3
P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, B. Sklenard, P. Coudrain*, S. Bobba*, H. Ben Jamaa, P-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. DeMicheli**, S. Deleonibus, O. Faynot, T. Poiroux (CEA-LETI, Minatec, *STMicroelectronics, **EPFL)
3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, the authors address the major challenges of 3D sequential: in particular, the control of molecular bonding allows them to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, they can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables bottom performance to be retained after top FET processing. They conclude that overcoming of these major technological issues offers a wide range of applications. Partitioning at the transistor scale 3D sequential integration enables both increasing density and performance without resorting to aggressive scaling. Its key technological enablers are molecular bonding and a low temperature top FET process which leads to the design of 3D transistors matching the targets of advanced nodes thanks to low access resistance, salicide, scaled EOT, optimized threshold voltage and mobility boosters.
Session 14, Paper 1
T. Nagata, H. Kanemaru, M. Ikegami, Y. Nagatomo*, R. Nakamura**, M. Handa**, K. Uchibori** (OKI Semiconductor Miyazaki Co., Ltd, *OKI Semiconductor Co., Ltd, **Citizen Finetech Iyota)
The authors explain that silicon on quartz (SOQ) technology is a great and promising technique for next generation mobile displays, enabling smaller and lighter liquid crystal displays for cell phones, near-eye displays, pico-projectors and view finders. And the technique can lead to fabricate SOQ device with high mobility and high reliability. The authors have successfully realized excellent optical transparent LCOS panels by combining a novel SOQ device with excellent panel technology. Mass production has begun.
Session 15, Paper 2
(D.J. Frank, L. Chang, W. Haensch (IBM T.J. Watson Research Center)
Consideration of energy and power constraints is critical in establishing roadmap projections for future generations of CMOS technology. The authors introduce a new optimization constraint, energy x power density, which better reflects actual design goals and compromises, and use it to evaluate technology scaling trends, highlighting differences from conventional expectations about scaling.
Session 15, Paper 5
Z. Ren, S. Mehta, J. Cai*, S. Wu, Y. Zhu*, T. Kanarsky, S. Kanakasabapathy, L.F. Edge, R. Zhang, P. Lindo, J. Koshy, K. Tabakman, P. Kulkarni, V. Sardesai, K. Cheng, A. Khakifirooz, B. Doris, H. Bu, D.-G. Park (IBM SRDC, *IBM T.J. Watson Research Center)
In this paper, the authors present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. They have demonstrated that they can fabricate low power (LP) CMOS with centered Vts and good Vt uniformity across wafer and wafer to wafer. Using this CMOS, they have fabricated low leakage and high performance ring oscillators (with delay ~20% faster than the standard 28 nm LP bulk). They have also obtained perfect 2.25M SRAM arrays, functioning down to Vdd of 0.5V, and have shown that a 10-level BEOL process has minimal impact on device stability.
Session 16, Paper 3
J. Cai, T.H. Ning, C. D’Emic, K.K. Chan, W.E. Haensch, D.-G. Park (IBM T.J. Watson Research Center)
The authors present NPN and PNP thin-base symmetric lateral bipolar transistors on SOI, a bipolar device architecture that will naturally integrate into an existing CMOS process flow without adding the complexity of vertical scaling present in the conventional high performance bipolar technologies. It overcomes the problems associated with conventional bipolar transistors including performance degradation at high current density and slow switching speed in saturation and fabricated samples show immunity to base-push-out effect. Primary applications for low voltage and memory applications are discussed. Modeling results show possibilities for high frequency analogy/mixed signal applications with fMAX >1THz as well as for digital applications at supply voltage of 0.5V with current lithography capability and SOI thickness of 20 nm.
Session 16, Paper 4
Experimental Evidence of Increased Deformation Potential at MOS Interface and its Impact on Characteristics of ETSOI FETs
T. Ohashi, T. Takahashi, N. Beppu, S. Oda, K. Uchida (Tokyo Institute of Technology)
The authors propose a new physical model of deformation potential (Dac, which determines the strength of electron-phonon scattering) in MOS structures. It is proposed and demonstrated that Dac increases sharply at Si/SiO2 interfaces within a range of a few nanometers. Since SOI has two Si/SiO2 interfaces, Dac effectively increases in ETSOI because of the contributions from both the interfaces. The increased Dac results in mobility degradation in ETSOI; whereas it contributes to an increase in stress-induced mobility enhancement in thinner SOI devices. They conclude that this finding is indispensable for designing nanoscale 3D FETs.
Session 16, Paper 5
First Demonstration of Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Combined with SiGe(:B) RSD: Drastic Improvement of Electrostatics (Vth, p tuning, DIBL) and Transport (µ0, Isat) Properties Down to 23nm Gate Length
C. Le Royer, A. Villalon, M. Cassé, D. Cooper, J. Mazurier, B. Prévitali, C. Tabone, P. Perreau, J.-M. Hartmann, P. Scheiblin, F. Allain, F. Andrieu, O. Weber, P. Batude, O. Faynot, T. Poiroux (CEA-LETI, Minatec)
The authors present the first successful integration of ultrathin (3.2nm) c-SiGe20% layers in Fully Depleted (FD) SOI pMOSFETs combined with SiGe30%(:B) RSD. c-Si0.8Ge0.2/SOI channels shift the threshold voltage by +120mV (with excellent variability) without SCE or DIBL degradation. Moreover the fabricated devices exhibit excellent variability performance and significant gain in Access resistance (-60%), transconductance and Isat (+170% & +220% @ L=23nm).
Session 18, Paper 1
A. Kerber, D. Lipp, M. Trentzsch, B.P. Linder*, E. Cartier* (GLOBALFOUNDRIES, IBM Research Division*)
The impact of time-dependent dielectric breakdown (TDDB) in MG/HK devices on SOI CMOS circuit functionality is examined using a novel fast PCI card based characterization setup. Detailed information on the role of the driver resistance on circuit failure is provided. By comparing breakdown in circuits with TDDB characteristics in discrete devices, it is shown that soft breakdown in cross-coupled inverter circuits is well correlated with soft breakdown in discrete devices. However, in all cases studied, it is observed that immediate circuit failure during high voltage stress is prevented by the resistance of the driver element. Implications of these findings on circuit lifetime assessment are discussed.
Session 18, Paper 6
E.G. Ioannidis, S. Haendler, A. Bajolet, T. Pahron, N. Planes, F. Arnaud, R.A. Bianchi, M. Haond, D. Golanski, J. Rosa, C. Fenouillet-Beranger, P. Perreau**, C.A. Dimitriadis***, G. Ghibaudo* (STMicroelectronics,*IMEP LAHC, **CEA-LETI, Minatec, ***Aristotele University of Thessaloniki)
The authors present the first thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies. Moreover, 28nm FD-SOI technology provides even better LFN variability (factor 2). Finally, circuit simulations have shown that the LFN variability has a serious impact on the SRAM cell operation.
Session 25, Paper 3
Chip-level Power-Performance Optimization Through Thermally-Driven Across-Chip Variation (ACV) Reduction
X. Yu, O. Gluschenkov, N.D. Zamdmer, J. Deng, B.A. Goplen*, H.S. Landis*, R. Logan, J.A. Culp, Y. Liang, M. Cai, W.-h. Lee, N. Rovedo, F.D. Tamweber, D.M. Lea, B.J. Greene, D.K. Slisher, A.I. Chou, H. Trombley*, S.V. Deshpande, W.K. Henson, A.C. Mocuta, K. Rim (IBM SRDC, *IBM Systems and Technology Group)
The authors note that standby leakage power has become increasingly important in semiconductor chip product design. Precise prediction of total chip leakage is of critical importance, but is very challenging to achieve. In this paper, the authors explore the quantitative connection between leakage uplift and ACV in depth at the chip product level, and demonstrate a product power-performance optimization in 32nm SOI by reducing product ACV with a process improvement. They propose a metric to capture the impact of ACV on chip-level leakage to quantitatively predict product-level leakage power using basic FET parameters, together with random and systematic intra-die variation. They demonstrated in hardware the means of monitoring components of variation, and applied these measurements to dramatically reduce product-level leakage with an improved thermal annealing process.
Session 25, Paper 5
J. Mazurier, O. Weber, F. Andrieu, O. Rozeau, M-A. Jaud, F. Allain, L. Tosti, L. Brévard, P. Perreau, C. Fenouillet-Beranger, F.A. Khaja*, B. Colombeau*, G. De Cock, G. Ghibaudo**, M. Belleville, O. Faynot, T. Poiroux (CEA-LETI, Minatec, *Varian Semiconductor Equipment Associates, **IMEP-LAHC, Minatec)
The authors present for the first time an extensive experimental study of the statistical variability of the drain current in 6nm thin undoped SOI MOSFETs. ID variations are found to be highly correlated with both threshold voltage and ON-state resistance fluctuations. Taking into account such correlations is of great interest for an accurate definition of spice model corners, and for optimizing FD-SOI technology. They also evidence the main technological sources of ID fluctuation.
Session 29, Paper 3
A. Niel, V. Gouttenoire, M. Petitjean, N. David, R. Barattin, M. Matheron, F. Ricoul, T. Bordy, H. Blanc, J. Ruellan, D. Mercier, N. Pereira-Rodrigues, G. Costa, V. Agache, S. Hentz, JC Gabriel, F. Baleras, C. Marcoux, T. Ernst, L. Duraffourg, E. Colinet, A. Andreucci, E. Ollier, P. Puget, J. Arcamone, E.B. Myers*, M.L. Roukes* (CEA-LETI, Minatec, *California Institute of Technology)
This work demonstrates for the first time VLSI-compatible nano/microfabricated, high-performance, portable multi-gas analyzers associating gas chromatography and Nano-Electro-Mechanical Systems (NEMS) detectors. The system presented in this paper features state-of-the-art experimental results in terms of limit of GC-mediated gas detection, and provides unique advantages in terms of compactness and portability. The fabrication process is straightforward and fully compatible with CMOS front-end processes: resonators are fabricated on the 160nm thick top silicon layer of 200mm SOI wafers (with a 400nm thick buried silicon oxide). NEMS are defined by two successive deep-UV (DUV) and e-beam lithography (eBL) steps with the same resist. The results of this work pave the way for the industrialization of ultra-miniaturized multi-gas analyzers.
Session 32, Paper 4
Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells Considering Variability and Temperature Sensitivity
V.P.-H. Hu, M.-L. Fan, P. Su, C.-T.Chuang (National Chiao Tung University)
A comprehensive analysis of leakage-delay, stability and variability of GeOI logic circuits and SRAM cells with respect to the SOI counterparts is presented. The UTB GeOI circuits show better power-performance than the bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices. For equal Ion design, the GeOI SRAM cells exhibit better µRSNM/σRSNM and smaller cell leakage variation.
Session 34, Paper 6
Thermal-Aware Device Design of Nanoscale Bulk/SOI FinFETs: Suppression of Operation Temperature and Its Variability
T. Takahashi, N. Beppu, K. Chen, S. Oda, K. Uchida (Tokyo Institute of Technology)
The self-heating effects of Bulk/SOI FinFETs are systematically investigated in terms of thermal resistance, for the first time. For the Bulk FinFETs, it is clarified that a) Bulk FinFETs have significantly lower thermal resistance, b)doping density fluctuation causes fluctuation in operation temperature, and c) the thermal variability can be suppressed by the extension length scaling. For the SOI FinFETs, it is demonstrated that the influence of interface thermal resistance is larger due to the relatively larger heat flow to the gate electrode.
Session 34, Paper 7
A. Bhoj, R. Joshi, S. Polonsky, R. Kanj, S. Saroop*, Y. Tan*, N.K. Jha** (IBM Research, *IBM, **Princeton University)
A comprehensive process/layout-independent TCAD flow is applied to FEOL/BEOL analysis/design of 32nm SOI SRAMs using, for the first time, iterative 3D TCAD capacitance extraction assisted by hardware data. Using the flow, FEOL junction capacitance is identified as the dominant factor affecting total bitline capacitance variation. Leveraging hardware data, the method is able to effectively predict other key capacitances (e.g., wordline) of generic layouts in the same process, thereby reducing the silicon footprint (cost) for test structures during early phases of technology development.
Session 34, Paper 8
Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
C. Xu, K. Banerjee (University of California)
The authors explain that Fully-Depleted SOI (FDSOI) technology boosts the opportunity to make 3-D ICs with ultra-high integration density, due to the short and tiny Through-Oxide Vias (TOVs), which are made after removing the entire silicon under the buried-oxide layer (using the BOX as an etch-stop). The work presentented in this paper develops for the first time compact physical models for the capacitance of the TOV and the coupling capacitance between TOV and active region in presence of periodical power lines. The models agree well with a 3D capacitance solver. The models are further used to analyze the threshold voltage variation in FDSOI MOSFETs. The results show that TOVs in FDSOI have larger Z11 (indicating higher performance), and that the impact of TOV in FDSOI on Vth variation is less (more) at high (low) frequencies, as compared to TSV in bulk-CMOS based 3-D ICs. These results provide important insights to TOV/TSV design and optimization in emerging 3-D ICs.