The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.
The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
Armed with the information from the 28nm bulk vs. FD-SOI benchmarking study, the SOI Consortium members then did new benchmark simulations at the 20nm node. This confirmed the trends they saw in silicon at 28nm. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):
- Peak performance was improved by 12 to 30 percent at constant total power, depending on design optimization efforts,
- Low-Vdd (0.7V) performance was improved by 65 to percent,
- Total power was reduced by 22 to 40 percent at constant maximum operating frequency.
Here’s the graphic that says it all. Follow the suggestions in the annotations to see how the power vs. performance trade-off works.
By adjusting Back Bias, FD can be changed from: High Performance Mode TO Leakage Saving Mode
To use this graph: pick any point on the lower, bulk line, then move horizontally to the left to see how much less power it will take to hit the same frequency with FD-SOI.
(a) Reverse back-bias allows you to cut leakage, here by a factor of 10
(b) This line is 20 nm FD-SOI with back biasing
(c) Or with back-biasing FD-SOI, you can hit over 269 MHZ using 120 mW at 1 V power supply
(1) This line is 20 nm Bulk
(2) This line is 20 nm FD-SOI
(3) Bulk takes over 130 mW to hit frequency of about 223 MHz with supply voltage of 1 V
(4) To hit the same with FD-SOI takes just over 100 mW and a supply voltage of just 0.9 V
(Courtesy: SOI Consortium)
About the study
STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.
Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog.