To paraphrase the song, “What a difference a day would make.” Searching to plug into the nearest power strip each afternoon, active smartphone users would certainly agree with that. But ST-Ericsson’s next-gen NovaThor chips on 28nm FD-SOI (available for design now), which are looking to get an extra day out of your battery, should put an end to that refrain.
In a recent article, PC Magazine’s Sascha Segan reports on a next-gen NovaThor (two 1.85GHz ARM Cortex-A9 processors). As he notes, “It’s speedy, but its real pitch is low power and low cost.” Marc Cetto, ST-Ericsson’s senior vice president for smartphone and tablet solutions explained to him that when moving to fully depleted silicon-on-insulator technology (FD-SOI), the two cores will run at extremely low power, especially when only low clock speeds are needed, which is actually most of the time.
Noting that the core strategy resembles nVidia’s “companion core” approach, Cetto explained to Segan that FD-SOI will let ST-Ericsson, “… run its main core at 400MHz like a ‘companion’ core without the extra cost and space of a whole extra core.” Furthermore FD-SOI will run more clock cycles at lower power, he continued, “…enabling ST’s chips to chug along at 1GHz at 0.6 volts while competitors need 0.9 volts for 1GHz.” That will amount to a 30 percent power savings, with even lower voltages possible at lower speeds.
How do they do it? ST-Ericsson’s principle engineer on the project, Valery Gravoulet, recently wrote an excellent series of tech blogs entitled FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor. His explanations and terrific graphs show why FD-SOI is blowing the bulk competition away.
Here’s a graph from his first blog, comparing the three 28nm technologies – high performance bulk (HP), low power bulk (LP), and FD-SOI – in terms of high performance (GHz) vs. supply voltage (VDD):
Gravoulet concludes, “So, over a large Vdd range (from 0.5V up to 1.3V), FD-SOI comprehensively outperforms existing bulk CMOS processes dedicated to mobile applications. This extra performance gain can be used either to increase peak performance or to operate at a lower Vdd for the same performance, saving dynamic power.” (For a complete explanation, click here to read part 1 of his blog.)
We’re now all coming to appreciate that our phones’ power usage comes in two flavors: the “dynamic” power needed to run the chip, and the “leakage” that’s just lost over time. In the second part of the Gravoulet/ST-Ericsson blog series (which you can read and see the graphs by clicking here), he first looks at the speed/leakage trade-off. He concludes: “…for the same leakage budget, FD-SOI at nominal voltage (1.0V) is systematically faster than either the LP process at nominal voltage (1.0V) or the HP process at nominal voltage (0.9V).
He then turns to power efficiency. As his graph shows, “for a given frequency , the total dynamic power consumption is always considerably lower – even if FD-SOI requires a slightly higher supply voltage than 28 “HP” to reach the target frequency. […] This behavior can be seen across the whole voltage and corresponding performance range demonstrating clearly that FD-SOI is the solution that gives the best power efficiency for mobile devices.”
Happily, we should be reaping the benefits of this move to 28nm FD-SOI in smartphones from ST-Ericsson customers (and they are fast building up an impressive list for the NovaThor line) early next year. And volume won’t be a problem, since they have both ST and a foundry lined up. (See slide #21 from the JM Chery’s presentation at the STMicroelectronics NV 2012 Investors & Analysts Day in NY a few weeks ago.)
Til then, anyone see a free outlet I can plug my charger into?