CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.
What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafers. What you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.
The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.
The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2. At this point in scaling, that gets you about two million gates – about eight million transistors. So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.
Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.
Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.
The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.
CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.
The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.
CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.
How it works
In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:
- NDA processing
- the design-kits linking CAD and processes, and related support
- Design submission, checking, and final database to the Fab
- Wafer sawing and Packaging
- Export license processing
- Chip delivery
Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.
For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.
These are real, leading edge chips and circuits we’re talking about. Here’s what you get:
- 28nm HK/MG FD-SOI with ultra-thin BOX and ground plane
- 10 Cu metal layers: (6 thin + 2 medium + 2 thick)
- Triple Well (Deep N-Well allows the P-Well to be isolated from the substrate)
- Single IO oxide + Single core oxide.
- Double VT: 1.0V Low Vt transistors (LVT) + 1.0V super Regular Vt transistors (RVT)
- Low Leakage (high density) SRAM using LP core oxide
- IO supply voltage: 1.8 V using the IO oxide.
- Ultra Low k inter-level dielectric
- 0.10µ metal pitch
- Self-aligned silicided drain, source and gate
- Poly and active resistors: Silicide protection over active areas for ESD protection
- CMP for enhanced planarization (on STI, Contacts, Metals and vias).
The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:
- CORE_LL: Low Power LVT
- CORE_LR: Low Power RVT
- CLOCK (LL and LR): Buffer cells and the same for clock tree synthesis
- PR: Place and route filler cells.
The IO cells Libraries include:
- Flip-Chip bumps
You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.
So this represents a real opportunity. Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.
FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip. Wouldn’t you like to give it a try?