Cadence announced the tapeout of a 14nm test-chip featuring an ARM Cortex®-M0 processor implemented using IBM’s SOI FinFET process technology.


Cadence announced the tapeout of a 14nm test-chip featuring an ARM Cortex®-M0 processor implemented using IBM’s SOI FinFET process technology. Leveraging Cadence tools and SOI’s built-in di-electric isolation for the ARM processor, SRAM memory and other blocks, a goal of the test-chip is to validate characterization data for FinFET-based ARM Artisan® physical IP.

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