To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.
To continue scaling CMOS technology, new approaches are needed and the industry is turning to ultra-thin body, “fully depleted” (FD) transistors. These may retain a planar architecture (Fig. 1b) or go tri-dimensional (Fig.1c), in which case current flows in vertical ‘fins’ of silicon.
In both cases, in contrast with traditional technology, the current between source and drain is only allowed to flow through a very thin silicon region, defined by the geometry of the transistor. In addition, such transistors can eliminate or alleviate the need for implanting “dopant” atoms into their channel.
The physics of FD transistors allows their behavior to be greatly improved – making it possible to continue creating more complex chips with better performance and, most importantly, with power consumption kept under tight control.
The semiconductor industry is introducing planar FD (also referred to as FD-SOI) starting at the 28nm node, with first IC product samples scheduled for the end of 2012. Tri-dimensional FD or FinFET, on the other hand, is expected below 20nm in foundries.
Wafers for fully-depleted technology
With FD technology, either planar or tri-dimensional, the transistors are either necessarily or advantageously fabricated on innovative silicon-on-insulator (SOI) starting wafers. These wafers consist of a very thin layer of crystalline silicon, separated from a silicon base by a high-quality (and optionally ultra-thin) oxide. Soitec’s Smart CutTM technology is used to produce them and is licensed to third-parties to ensure multi-sourcing options.
Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for the planar and FinFET implementations of FD transistors. Two different wafer product lines are available to serve the needs of these two technology flavors.
FD-2D – An early and evolutionary path to fully-depleted technology
Planar FD technology puts tight requirements upon starting wafers to deliver all its benefits: for example, top silicon layer thickness must be uniform to just a few Angstroms. Today, Soitec’s FD-2D product line meets these needs in a cost-effective way and makes planar FD technology a reality.
Figure 2 outlines the structure of a transistor fabricated from an FD-2D wafer. For the 28nm technology node, the buried oxide thickness has been set to 25nm; the ultra-thin top silicon allows fabrication of transistors with 5nm to 8nm silicon under the gate. Future generations can leverage even thinner buried oxide layers, contributing to making this technology scalable to subsequent nodes.
By enabling a planar implementation of fully depleted technology, these wafers offer the opportunity to access the benefits of FD today – there is no need to anxiously await FinFET and the 16nm/14nm technology node. Adopters of planar FD are announcing very substantial performance and leakage gains as well as impressive improvements of energy efficiency, along with exceptional performance maintained at very low power supply [Ref.1-3].
Owing to the great compatibility of planar FD with conventional CMOS, designers retain the flows and tools they would use with the latter. Furthermore, chip manufacturers use the same production lines as well as extremely similar process steps. Finally, different studies indicate that the cost of ownership of chips based on planar FD is extremely competitive compared to any alternative.
FinFET – Transition facilitated by innovative FD-3D wafers
A FinFET transistor consists of one or several fins of silicon, electrically isolated from the substrate, around which the gate wraps.
One solution (Figure 3a) to manufacture FinFETs consists of starting from a traditional bulk silicon wafer and completely handling fin creation and isolation through the CMOS process.
The alternative (Figure 3b) is to start from a “FinFET-friendly” wafer such as Soitec’s FD-3D, which pre-defines some of the fin characteristics and, with its buried oxide, natively embeds the electrical isolation, thus simplifying the CMOS process.
Specifically [Ref. 4-5], FD-3D wafers help obtain clearly defined and reproducible fin height and width, consistent alignment of gate, source, drain and channel, and provide optimal isolation of each fin. In addition, it is possible to implement undoped fins if desired – thus cutting variability related to random dopant fluctuations.
Overall, and especially as dimensions will continue to shrink beyond the 16nm node, FD-3D wafers offer to facilitate control over key parameters of FinFETs as well as simplify the fabrication process. They represent an opportunity for chipmakers to make the most of FinFET technology in terms of power/performance ratio and leakage power at chip level. They are also a worthwhile proposition to reduce the industrialization challenges and optimize the total cost of ownership.
Looking beyond the 10nm node, technology based on germanium and III-V compounds is being actively researched. In parallel, the transition of leading-edge chip production to 450mm diameter wafers is expected for the end of this decade.
In this context, the Smart Cut™ layer transfer technology for manufacturing innovative wafers may again prove extremely valuable by enabling independent control over various optimization knobs. For example, transferring a thin layer of high-quality, optimized III-V material onto a low-cost handle wafer (silicon or other), with an optimized interfacing layer, could be an interesting option.
Fully depleted silicon technology is coming. The question is how fast and how easily this transition can be accomplished: innovative wafers provide part of the answer.
With FD-2D, they enable a planar implementation, providing the semiconductor ecosystem with an early and low-risk path towards optimal performance and power efficiency across all use cases, as soon as the 28nm node.
With FD-3D, they can help efficiently address some key challenges of FinFET technology and make the most of it.
Looking further ahead, the Smart CutTM technology will continue to simplify the implementation of the next silicon technology breakthroughs.
[Ref.1] White Paper, “Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond”, STMicroelectronics – http://www.soiconsortium.org/about-soi/white-papers.php
[Ref.2] ST Ericsson Technology Blog, May 2012: “FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2”, http://blog.stericsson.com/blog/2012/05/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-%E2%80%93-part-2-2/
[Ref.3] “MWC ST-Ericsson Media & Analyst Briefing”, February, 2012 – http://www.stericsson.com/investors/Analyst-Event-Presentation-MWC-12.pdf
[Ref.4] « SOI Value in IBM Silicon Technology », Oct.2011 – http://www.gsaglobal.org/3dic/docs/20111019_IBM_SOI_Value_GSA.pdf
[Ref.5] “SOI versus bulk-silicon nanoscale FinFETs”, Jerry G.Fossum et al., SSE Volume 54, Issue 2, Feb. 2010.