FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, and can compromise power, performance, and manufacturability.
Here we briefly explore several important aspects regarding the benefits of employing Fin-on-Oxide (FOx) isolation of the active FinFET channel region from the substrate semiconductor over that of first-generation bulk FinFETs, and examine how FOx as enabled on an silicon-on-insulator (SOI) wafer is well-positioned to deliver optimal FinFET value in 2nd Generation CMOS technology.
Isolation-Related Manufacturing Challenges
In a bulk a FinFET process, fins are formed in bulk silicon, an isolation oxide (SiO2) is deposited in the trenches between fins, and then etched back to expose some portion of the fins, thus defining the baseline active fin height.
Ideally the fins formed would be vertical and of uniform width (TFIN) to best realize uniform FIN turn-on (from top to bottom of the fin). Practically, however, there are two process issues that drive a need to taper the fins, resulting in ‘triangular’ shapes. The first issue is that the cavities between fins must be filled without forming voids, which necessitates a fin sidewall that is less than 90 degrees. Such voids, if formed, are capable of killing yield (such voids can subsequently fill with either source/drain materials or gate materials, causing short-circuits). The second issue is driven by the need to clear the sidewalls of the fins following (dummy) gate formation, prior to source/drain epitaxial growth. These spacers must be removed from source and drain regions of fins by an anisotropic etch and hence more gently sloped fins, require less over-etch. Some over-etch is always required since any remaining spacer material on an occasional fin can block the formation of the source and drain regions, again killing yield. Extension of over-etch times erodes the isolation oxide adjacent to source and drain fin regions (the channel region is protected by the dummy gate) and hence (vertical) misregistration of the source/drain regions to the gate is worsened, requiring further steps to avoid sub-channel leakage in the fin. The net of this is that a bulk fin employing well/ junction isolation brings with it some intrinsic compromises in fin shape/morphology.
Power/Performance/Leakage Drives Need for Oxide Isolation of Fin
The bulk FinFET includes a ‘sneak path’ from drain to source in a portion of the fin that extends below the channel. Illustrated in Figure 1 are three ‘alignments’ of importance to well-isolated FinFET designs.
Ideally, the source/drain depth, YSD, the channel-stop depth, YCS, and the gate-edge depth, YGE, would be identical with an abrupt doping step in the fin, just below the gate, to cut off the ‘sneak path.’ Practically, such a structure is not possible, and so, even for an ideal, vertical fin shape, doping in the sub-fin must be sufficiently high to cut off this leakage. In this case one could simply dope the fins uniformly; the doping level required is greater than that needed to achieve a given channel leakage without the sneak path. Penalties for product design, illustrated in Figure 2, ensue.
The maximum operation voltage is limited by maximum allowable electric field in the gate dielectric. Higher doping in the channel results in higher electric fields in operation in a bulk fin, and hence there is an associated reduction in Vmax also illustrated in Figure 2. Additionally, VT variations are increased by this higher doping, and Vmin is increased, for SRAM and other matching-critical circuits. Both ‘Turbo-mode’ performance and low-power mode operation suffer in a bulk-isolated FinFET.
Thus far we have taken the case of ideal fin morphology; in practice, bulk-isolated fins present a fin channel with a wider base and the resulting poor gate control requires an even higher doping in this region. The doping at the base of the fin must be sufficient to elevate the local VT by 100-200mV above that of the upper, narrower, portions, in order to avoid excessive device leakage. The output conductance is severely degraded by the delayed, soft turn on of the composite fin. Effective drive current is lost, in this example on the order of 15%, and additionally analog-like high-speed circuits, such as High-Speed I/O are compromised.
The Critical Role of Active Fin Height
Whether on bulk or SOI, FinFETs introduce one fundamentally new behavior for CMOS products, that of (active) fin height (Hfin) variation. In a FinFET transistor, the WEFF varies nearly in proportion to Hfin. Large (wide) transistors will vary in drive strength nearly as much as narrow transistors, since the ‘wide’ FETs simply consist of a larger number of the same base fin. As Hfin varies from die-to-die due to manufacturing variations, the WEFF of every transistor varies by the same percentage, not the same number of nanometers, as in planar CMOS. This means that active power and performance of a product can be strongly modulated by Hfin, and the tolerances of the bulk manufacturing process can be driven by many challenging-to-control factors, such as across-wafer uniformity, process chamber uniformity, and local design-driven density and proximity issues. The die-to-die variation can appear as an Fmax/Power CLY loss.
SOI as a Means to FOx
While dielectric isolation has been demonstrated on bulk wafers, these schemes continue to lack Hfin control and add cost to the bulk integration for FinFETs. A FinFET process based on an SOI wafer is cost neutral compared to a bulk-isolated Fin with the additional SOI wafer cost easily equaled by the additional bulk process complexity.
SOI offers ultimate Hfin control, with the SOI layer itself defining Hfin. No pattern sensitivities enter, as the active silicon layer is formed unpatterned across the entire substrate. Isolation is automatic and no extra process steps, beyond those required for the transistor formation, are required. Thus within-die and die-to-die variation of Hfin is much less than any currently known alternative, leading to the lowest Vmin, power, and highest Fmax, and CLY for FinFET CMOS.
Misconceptions Surrounding FinFETs on SOI
Strain: Mechanically straining the silicon channels can enhance both hole and electron mobility. Direct techniques for imparting fin strain apply equally to fins on either substrate. One technique employed, embedded SiGe for pFETs, does present a small gain in attainable strain of up to 6% in bulk-fin pFET drive current, amounting to a 3% decrease in a CMOS critical path delay. This gain for the bulk case is, in reality, eroded, if not reversed, by an increase in leakage current from the source/drain region recess beneath the gate, required to realize the added strain. The final result is that an academic gain of up to 3% might be afforded a bulk fin over its SOI counterpart, but when other strain techniques and short-channel degradations are considered, even this benefit vanishes.
Self-heating in SOI FinFETs is very similar to that in planar SOI MOSFETs, and as such, the issues and solutions are well understood at a practical product-applications level. For digital circuits, self-heating is not a consideration, as the short-transient energy dissipated from a single transition is absorbed by the heat capacity of the device with a negligible temperature rise. For circuits in which duty factors are sufficiently high, well-established CAD techniques from planar SOI offer solutions. A narrow sliver of silicon connecting a bulk FinFET to the substrate does reduce the degree of self-heating, but similar CAD requirements in product design remain. Other aspects surrounding self-heating include effects on device and interconnect aging, and here again, the techniques practiced over several generations of planar SOI enable design capability to assure the required product reliability in the field.
Wafer cost and supply: SOI FinFET technology enables a competitive high-volume presence in the market. The steps required to isolate fins on a bulk substrate add considerable complexity and process cost which easily negates any savings in initial wafer cost. Furthermore, the simpler process with SOI FinFETs results in shorter turn-around time. The reduced variability on SOI returns improved yield, and recent announcements by major wafer suppliers have assured a volume supply chain.
SOI Market Value
In addition to the quantitative advantages of SOI-based FinFET described above, the very nature of the near-ideal isolation provided opens many doors to diverse applications. IBM has enjoyed a significant advantage in processors through the integration of embedded DRAM, enabled by SOI isolation, providing 3X net memory density advantage and similar power reduction. RFCMOS, now exploiting SOI in mature nodes, will continue to find high value in SOI FinFETs due to lower parasitic capacitances, reduced (inductive) substrate losses, and radically lower substrate-driven harmonic generation (and other product mixing). A wide range of voltage islands are naturally available, both above and below substrate/ground, without the complexity of triple wells and the restrictions/penalties associated with latch-up avoidance. Automotive, and other very high-temperature environments present no barrier in SOI-based FinFETs.
The value proposition of SOI presented in PDSOI becomes even stronger in FinFET technology, as clearly described above. Furthermore, the design drawbacks of non-standard timing tools and added cost, which presented some barrier in PDSOI vanish as we migrate to FinFET technology, and portability of products from bulk to SOI FinFET designs is very high. As SOC FinFET products are introduced, it is expected that the benefits of dielectrically isolated fins, and in particular, the SOI implementation for this isolation, will prove a clear winner in the market place due to lower variability, lower power, simpler designs and greater flexibility for integration of multiple product needs on chip.