Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.
What do you see as the FD-SOI benefits for chip designers?
- Lower SRAM Vmin for retention and lower operating Vmin for Logic
- Wider range of Voltage operation for performance/power trade-off
- Total dielectric isolation equates to lower capacitances, lower leakage, and latch-up immunity
- Ultra-thin silicon film provides excellent electrostatic control and optimum transistor performance
- Back-bias control gives an additional speed boost
- Simple planar process using same front end and back end as our 28SLP process, which means fewer process steps and fewer masks, helping to absorb the additional substrate cost
What are your plans for making FD-SOI available to your customers?
We are the manufacturing partner for ST’s FD-SOI technology. We also are planning to offer the technology to other customers who may be interested, but we have not announced details yet. We are the only pure-play foundry with deep experience in both bulk and SOI technologies, which allows us to offer a broader range of technologies at advanced nodes.
Can you elaborate on the “maximum” version of FD-SOI — tuned for specific applications — what sorts of things would those be?
Examples of features in the Maximum version of FD-SOI:
a. Back-bias capability on logic for higher performance
b. Denser SRAM by taking advantage of lesser variability of Fully depleted device
c. Base Vts tuned for specific applications (performance vs power trade-off)
And the “minimum” version — a simple and “out of the box” FD-SOI technology — who/what is this for?
a. No Back-bias supported
b. All SRAMs are foot-print compatible to 28SLP
c. Fully depleted device offers better Vmin and power advantages: Optimized for Mobile Applications
Are there any special logistics in terms of the PDK, IP, etc?
a. PDKs are similar to bulk CMOS, except the models will support a 4-terminal device for Back-bias
b. In the base version (termed as minimum version above), IP’s Physicals are fully compatible with bulk CMOS, but would require electrical re-characterization to take advantage of improved FD-SOI device characteristics
c. In the extended version (termed maximum version above), IPs will be designed to take advantage of Back-bias for better performance/power trade-offs in specific applications
What is the next node, and when will that roll out?
See slide 8 of [this] presentation: