Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing


For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS processing to deliver high-performance, high-volume RF devices that meet the cost and performance goals of the most competitive markets. The development of UltraCMOS being a laboratory curiosity, to becoming the RF Front End (RFFE) process of choice, has included two decades of process development, breakthrough innovations and key inventions.

Highly Insulating Substrate

The use of sapphire as a highly insulating substrate for RF Silicon-on-Insulator (RF SOI) CMOS processing began when visionaries took advantage of sapphire’s exceptional properties and overcame the limitations that previous researchers had encountered. The properties of synthetic sapphire, or aluminum dioxide (alumina), include 1014 ohm/cm resistivity, making it a near-perfect insulator. Additionally, sapphire has good thermal properties. These combined attributes make sapphire well suited for use as a semiconductor substrate.

As shown in Figure 1, Peregrine Semiconductor’s UltraCMOS technology involves combining silicon with the highly-insulating substrate without incurring major defects, resulting in a highly-manufacturable semiconductor process. This process can be implemented in any standard CMOS foundry, leveraging existing CMOS capacity and avoiding substantial investment, while maintaining technology leadership.

UltraCMOS process
Figure 1. The UltraCMOS process, an advanced HR-RFSOI technology, can be implemented in any standard CMOS foundry.

UltraCMOS technology was first used for Phase-Locked Loop (PLL) products designed for the infrastructure market, as well as space applications that relied on the inherent radiation tolerant (rad-hard) performance of sapphire, as well as the latch-up and Single Event Upset (SEU) immune UltraCMOS process.

progressive improvement in RonCoff
Figure 2. The progressive improvement in RonCoff established by the STeP2 process technology is maintained, today.

The key to developing the platform that has provided a more than 20% year-over-year (YOY) performance improvement is attributed to adapting Moore’s Law, plus internal knowledge of device physics. As opposed to simple scaling, significantly improving the basic Field Effect Transistor (FET) performance is achieved by reducing the on resistance of the channel, or improving the breakdown voltage, or the linearity, of the device. One performance metric for the FET is based on the product of the resistance from the “on” state and capacitance from the “off” state that provides a Figure of Merit (FOM) for the process technology, called “RonCoff.” For UltraCMOS-based products, an improvement in RonCoff relates directly to the improvement of the device performance and size reduction.

For Peregrine, high-volume production began with RF switch products based upon its Semiconductor Technology Platform 2 (STeP2). As shown in Figure 2, from the 0.5-µm STeP2 process in 2004 to STeP5 in 2012, Peregrine has been able to maintain a 20% YOY improvement in RonCoff. The combination of the process, device, and modeling capabilities that allow fabrication in any standard CMOS facility has proven to be a successful, sustainable strategy for RF performance, enabling fast-track RFFE performance and an accelerated roadmap.

Semiconductor Technology Platform (STeP) 8: A Major Step Forward

Continuing down the process roadmap shown in Figure 2, 0.25 µm, bonded(1) STeP8 technology provides the largest improvement in RonCoff performance for a 12-month window. Instead of obtaining a 20% YOY reduction, the development team’s efforts achieved a 36% YOY decrease within one year of the announcement of the previous generation of STeP technology, STeP5. In addition to greatly exceeding expected performance targets after ten years of process of development, this demonstrates that the STeP roadmap is sustainable for even further improvements. With STeP8 process technology at 250 nm, there is a long runway led by digital technologies that are now at 22 nm.

Linearity

The industry and 3GPP standards body specified the input third order intercept point (IP3) as the required degree of linearity, which helps to avoid interference with other devices on the network. The modelers, process engineers and designers at Peregrine determined where the nonlinearities were occurring and invented HaRP™ technology to significantly improve the harmonic performance of their products. This device-level technique increases the IP3 linearity and improves the switch linearity of UltraCMOS products by more than 10 dB (an order of magnitude), on average. Figure 3 illustrates the performance improvements that HaRP technology enhancements enable.

HaRP™ technology-enabled prototype RF switch versus a switch without HaRP technology enhancements
Figure 3. The first HaRP™ technology-enabled prototype RF switch versus a switch without HaRP technology enhancements demonstrate the technology’s ability to achieve 3rd harmonic phase requirements at 5:1 VSWR (conditions: 3fo, Tx1, 33.5 dBm, 2.6V, 915 MHz).

The HaRP invention established Peregrine as a leading provider of high-performance RF switches in the market. Since the technology is applied to GSM/WCDMA switches, this rapidly led to very high-volume production. Peregrine applied the implementation of the device-level technology into its entire RF product portfolio, beyond switches. This capability led to an accelerated STeP process roadmap designed to optimize and advance HaRP technology performance.

UltraCMOS® STeP capabilities
Figure 4. UltraCMOS® STeP capabilities meet the ever-increasing IIP3 linearity requirements of 2G, 3G, and 4G networks.

According to the Shannon limit (the theoretical maximum information transfer rate of the channel), the more linear the components are, the higher the data rates that can be achieved in the communication channel. As shown in Figure 4, STeP8 has demonstrated input IP3 (IIP3) performance that exceeds 77 dBm.  With the communication industry’s demand for improved linearity, the ability of STeP2 to meet/exceed 2G requirements of 55 dBm, STeP3 to meet 3G requirements of 65 dBm, STeP5 to exceed 4G LTE 72 dBm requirements, and STeP8 to provide even greater performance allows continued progress in this critical area.

STePs to Higher RF Performance

Peregrine has demonstrated a path for advancing UltraCMOS STeP technology to meet market requirements. To meet the industry’s projected 78% compound annual growth rate (CAGR) from 2011 to 2016, expanded network capacity is expected to come from improved radio link performance, Multiple Input/Multiple Output (MIMO), Carrier Aggregation (CA), new infrastructure, and new spectrum. Peregrine Semiconductor expects to deliver UltraCMOS RFFE products to meet all of these requirements. STeP10 devices are currently in laboratory evaluation and the results look promising to follow this path, with no foreseen limits to advancing the technology further.

(1) bonded silicon on sapphire (BSoS) substrates from Soitec

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