At a high-profile ceremony near Grenoble last month, FD-SOI got a big boost – a 600 million Euro boost (about $800 million), to be exact. Top French ministers gathered at the STMicroelectronics site in Crolles (near Grenoble) for the launch of the Nano2017 Research and Development program. Also present at the ceremony were key partners of ST for the Nano2017 R&D program including CEA-Leti and IBM.
Nano2017 is a five-year public-private strategic R&D program, targeting key technologies: FD-SOI (for low-power, high-performance processing), next-generation imaging (sensors and image signal processors – some of which ST’s putting on SOI) and next-generation embedded non-volatile memories.
It’s led by ST and also includes several university research teams, material and equipment manufacturers, vendors and CAD intellectual property specialists, system integrators, and other European stakeholders and Small and Medium Enterprises (SMEs). The project is supported by French national, regional and local authorities as well as by the European community through the ENIAC Joint Technology Initiative (JTI). (Funding for the program is subject to approval by the European Commission.)
The 600 million Euro investment in the program from the French government is in addition to the 3.5 billion Euros that ST and partners have already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).
The French government says that Nano2017 will make Grenoble one of the three pillars (along with what could be considered the other European SOI capitals: Dresden/GlobalFoundries and Eindhoven/NXP) of the European Horizon2020 program, which launches in January 2014. It will also help ST double production capacity of the Crolles fab, which is certainly good news for the greater SOI ecosystem.
ARM CEO’s a Fan
In other good FD-SOI news, Electronics Weekly’s David Manners recently reported that ARM’s new CEO, Simon Segars, is an FD-SOI enthusiast.
According to Manners, Segars said, “We have been looking at FD-SOI, it’s a very neat solution to providing more performance and lower power in a planar transistor”.
“I’ve seen some of the results ST have achieved and they’re really impressive”, Segars continued, “and I’ve seen chips running on the bench and, from the performance and power perspective, it’s very impressive”.