SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!


IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)
(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)
(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight
(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

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