SOITEC and UCL boost the RF performance of SOI substrates

Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of wireless communication standards.

In 2003, UCL demonstrated the possibility of further improving the RF performance of HR-SOI substrates by minimizing or even eliminating the so-called parasitic surface conduction inherent in any oxidized silicon substrate [1]. UCL proposed a figure of merit, the effective resistivity, which helps compare the RF performance of various technological solutions as well as monitoring in-line the quality of fabricated substrates.

The effective resistivity accounts for the wafer inhomogeneities (i.e., oxide covering and space charge effects) and corresponds to the resistivity that a uniform (without oxide nor space charge effects) silicon wafer should have in order to sustain identical RF substrate losses. In other words, it is the value of the substrate resistivity that is actually seen by the coplanar devices.

Therefore, comparing the wafers in terms of their effective resistivity allows us to isolate the performance of the substrate by eliminating series losses and skin effect inside conductors. The interest of the effective resistivity as a factor of merit is not limited to the monitoring of the RF quality of the fabricated substrate but it is also a physical parameter which is used by RF designers to properly model the impact of the substrate.

A new substrate is born

Soitec and UCL have been working together to identify the technological opportunities to still further improve the high-frequency performance of commercially available HR-SOI substrates. Thanks to the introduction of an engineering substrate handle, Soitec can now provide a new flavor of HR-SOI called eSI, for enhanced Signal Integrity (see Figure 1) substrate (previously named Trap Rich) with a measured effective resistivity as high as 10 [2].

New generation of HR-SOI substrate
Figure 1. A new generation of HR-SOI substrate: enhanced Signal Integrity (eSI) (Image courtesy of Soitec)

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along CPW lines and purely capacitive crosstalk similarly to quartz substrate. It has been demonstrated that the presence of a trap-rich layer does not alter the DC or RF behavior of SOI MOS transistors [3].

Besides the insertion loss issue along interconnection lines, the generation of harmonics in the Si-based substrates has been investigated. HR-SOI substrate presents reduced harmonics compared with standard SOI substrate and the introduction of engineering eSI substrate handle leads to harmonics levels well below the wireless communication systems [4] (see Figure 2).

Harmonic distortion along a 2,146 µm-long CPW line
Figure 2. Harmonic distortion along a 2,146 µm-long CPW line when a signal at 900 MHz is injected at the input for a trap-rich HR-SOI wafer from SOITEC. The specification (specs straight line) for the harmonic distortion corresponds to that of RF switches for GSM/EDGE transmitter modules [5].
The improvement of the HR-SOI substrate brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors, for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc.

Thanks to the introduction of eSIengineered substrate handle, the HR-SOI substrate can really be considered as a lossless Si-based substrate. eSI HR-SOI technology opens the path to further system integration in the Front End Module space as well as even more complex mixed-signal System-on-Chip (SoC).



A BIT OF HISTORYFor over 15 years, UCL’s Raskin research group has been developing high-frequency characterization techniques, which are today widely used by industry as well as other research teams. The group has been measuring advanced MOS devices (fully and partially depleted SOI transistors, FinFETs, Ultra-Thin Body and BOX (UTBB) devices, silicon nanowires, Junctionless multiple gate MOSFETs, etc.) from international research centers and companies.

UCL's Welcome platform
Figure 3. UCL’s Welcome platform: electrical characterization room of 350 m2.

The experimental platform known as “Welcome” at UCL (see video) is equipped with the latest electrical measurement equipment covering on-wafer measurements over a wide frequency range (DC up to 110 GHz) and temperature range (4K up to 300°C). UCL also has 1,000 m² in cleanroom facilities, including an SOI CMOS process (see Figure 4).

UCL's Winfab
Figure 4. UCL’s Winfab has 1000 m² of class M1 cleanroom facilities

In 1997, Prof. J.-P. Raskin presented pioneering work on the RF performance of HR-SOI substrates [6]. This paper demonstrated the great interest of HR-SOI substrates to reduce RF losses as well as the crosstalk in Si-based substrates.

In 2005, the team demonstrated the possibility creating HR-SOI substrates characterized with an effective resistivity as high as 10 thanks to the introduction of a high density of traps at the BOX/HR-Si handle substrate [3]. Those traps originated from the grain boundaries in a thin (300 nm-thick) layer.

In 2011, with former PhD student Dr. Mostafa Emam, the team launched a spin-off company, Incize (, which offers RF electrical characterization services.


[1]    D. Lederer, F. Brunier, C. Desrumaux and J.-P. Raskin, “High Resistivity SOI substrates: how high should we go?”, IEEE International SOI Conference, Newport Beach Marriott Newport Beach, CA, USA, September 29 – October 2, 2003, pp. 50-51.

[2]    K. Ben Ali, C. Roda Neve, A. Gharsallah and J.-P. Raskin, “RF SOI CMOS technology on commercial trap-rich high-resistivity SOI wafer”, IEEE International SOI Conference – SOI’12, Napa, CA, USA, October 1-4, 2012, pp. 112-113.

[3]    D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity”, IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, November 2005.

[4]    C. Roda Neve and J.-P. Raskin, “RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 924-932, April 2012.

[5]    M. Carroll et al., “High-Resistivity SOI CMOS Cellular Antenna Switches,” CSIC 2009, October 2009, Greensboro, NC, pp. 1-4.

[6]    J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk reduction using SOI technology”, IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252-2261, December 1997.

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