SOI: Looking Back Over a Year of Moving Forward (Part 2, RF-SOI & SOI-FinFETs)

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As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.

But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year.  In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.

 

The RF-SOI Juggernaut

SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.

In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.

In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.

In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.

Peregrine_ultracmos_waferLoRes
(Photo: Business Wire)

In November, Peregrine Semiconductor announced that it has shipped its 2 billionth RF chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

 

 

 

eSI_SoitecUCLwafer
A new generation of HR-SOI substrate:
enhanced Signal Integrity™ (eSI)
(Image courtesy of Soitec)

In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications.  Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.

 

 

14nm SOI-FinFETs Get Real

In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs.  SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)

They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.

For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.

ASN_IBM_SOI_FinFET

Representative bulk-based (junction-isolated) and SOI-based (dielectric-isolated) fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET. (Courtesy: IBM)

 

 

Manufacturing a FinFET on SOI also enables a more ideal fin profile.  In turn, this near-ideal shape delivers performance well in line with the “theoretical”  benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.

IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.

The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.

So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!

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