IP for FD-SOI: Examples from ST

Post on :

Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog.

Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here to view it).

Memory

FDSOI_memory

Memory is the proverbial canary in the coal mine for chip designers. To run reliably, pairs of transistors can’t be mismatched – and this becomes more critical with the lowering of the supply voltage (Vdd), nowhere more so than in memory. FD-SOI decreases mismatching by 40% compared to low-power (LP) bulk, and decreases leakage by a factor of 8.  Soft error rates (SER) are 100x better in FD-SOI than in bulk.  And of course, being able to run at lower voltages can make a significant contribution to battery savings in portable devices.

Cores

FDSOI_Core_Efficiency

In the example of a dual ARM A9 subsystem architecture, ST’s IP is used to generate programmable body voltages, enabling a CPU to run at 300 MHz with a 0.5V supply voltage. Increasing the supply voltages increases the performance: up to 2.3 GHz at 1V, and on to 3 GHz at 1.34V. And with forward body biasing (FBB), which is only possible in FD-SOI, you get 1GHz at 0.6V when you need it.

 

Dynamic process scaling, thanks to extended body biasing, allows dynamic switching between high-speed and static-power optimizations. In a multi-core context the effects are dramatic.

FDSOI_multicore

 

Ultra-Low Voltage Apps

For things like medical devices and Internet of Things (IoT) apps, the ultra-low voltage design enabled by FD-SOI should be a key differentiator.

Sans titre

Analog

The presentation shows that ST is particularly pleased to emphasize what analog designers can do with FD-SOI. For example, in a switch the resistance ratio between on and off (Ron/Roff) is 10x better in FD-SOI than in bulk or FinFETs.  Power signal gains are improved by 6x without using pocket implants, and matching is better in short-channel devices because there is no channel doping.

ST_IP_FDSOI_analog

Here at ASN, we’ll have lots more good news and useful information coming your way from the FD-SOI design community in the weeks and months to come. So if you haven’t signed up for a free subscription* yet, now’s the time! Just click here and fill in the form.

 

*Please note that we do not share our subscription list with any third parties.

 

 

Leave a Reply

Your email address will not be published. Required fields are marked *