By Handel Jones
IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry. The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.
We conclude that:
- at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
- the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.
Here is a brief summary of our findings.
High volume applications need lower cost per transistor in order to use the new generation of process technologies. It is, consequently, appropriate to evaluate the options for continuing the pattern of lower cost per gate, with the analysis of different technology options.
After the 28nm node, the decreasing cost-per-gate trend with reduction in feature dimensions for bulk CMOS is reversed: at 20nm, cost-per-gate starts to increase rather than decrease.
Cost Per Gate Reduction Trends
The impact of not reducing cost per gate is one of the most serious challenges that the semiconductor industry has faced within the last 20 to 30 years. It is, consequently, appropriate to evaluate whether other options are available that can allow scaling to 20nm and smaller feature dimensions to be effective in cost and power consumption because of the large financial impact on the semiconductor industry of not continuing with Moore’s Law.
Wafer Cost Analysis
Our analysis considers depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.
Already at 28nm, the wafer cost is lower for FD-SOI than for bulk HKMG CMOS, although with a relatively small difference. The key reason for the lower cost of FD-SOI is the smaller number of mask and processing steps.
The cost analysis is based on eight-layer metal and 3Vt levels. The following graph is built from the more detailed analysis in our report.
Furthermore, while the difference in total yielded wafer cost at 28nm and 20nm is not very large, it is very important to remember that the FD-SOI technology has the added advantage of providing significantly lower leakage and higher performance than the bulk CMOS.
The reality is that performance of 28nm FD-SOI is 15% better than 20nm bulk CMOS and extends the lifetime of the 28nm technology node. Lower cost, lower power consumption, higher performance, the conclusions are clear.
The situation is even more compelling at 14/16nm.
The wafer cost for 14nm FD-SOI is 18.4% lower than 16nm FinFET. A key factor contributing to the high cost of FinFET wafers is that of the extensive inspection steps required to ensure high yield and high reliability. A number of wafer processing steps need to be tightly controlled and monitored with the processing of FinFET structures. The result is that depreciation cost per wafer for FinFET structures is significantly higher than for FD-SOI.
Note: the generation we call 20nm FD-SOI in our report is called “14FD” by ST Microelectronics, as they also position it as a competitor to 14/16nm FinFET.
While wafer cost is an important factor, die cost is a more vital factor for most companies. Our analysis includes yielded wafer cost, gross die/wafer and yield.
At 28nm, FD-SOI has higher yield, slightly lower die cost (3%) and 30% lower power consumption than bulk CMOS. At 20nm, FD-SOI die cost is 13% lower than bulk CMOS, has higher yield, and is expected to provide 40% lower power consumption.
At 14nm/16nm, the FD-SOI die cost for a 100mm2 die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.
The lower cost of the FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI at this technology node.
However, despite the fact that FD-SOI is clearly more cost effective, large investments are being made by the pure-play foundries in 14/16nm FinFET wafer processes, and while FinFETs will be needed in the future, the issue is timing. It is clearly in the interest of the fabless industry to pay lower die prices, and collaboration with the foundry vendors is needed in this arena. The power structure in the industry has moved too much in favor of the provider rather than the user.
For the fabless industry, the key requirement for FD-SOI is to establish supply chains that can support the participation in high-volume end markets. The fabless companies need to be much more active in ensuring that their needs are being satisfied.
Strategic Considerations Within the FD-SOI Supply Chain
Strategic considerations within the FD-SOI supply chain include the following:
- Complex, working products with FD-SOI at 28nm have been demonstrated by STMicroelectronics with significant performance and power consumption advantages compared to bulk CMOS.
- The supply chain for FD-SOI starting (i.e., raw) wafers is in place (by Soitec, SunEdison, and Shin-Etsu Handotai (SEH)) and can be expanded rapidly to provide the required wafer capacity if a demand environment is established.
- The use of body biasing provides significant performance and power consumption advantages for FD-SOI. Body-biasing methodologies for FD-SOI can use EDA tools that have been developed for bulk CMOS technology. Also, design flows for FD-SOI are effectively identical to those for bulk CMOS. However, it is important for the EDA vendors to become more proactive regarding the potential opportunities for FD-SOI.
- Libraries and basic IP developed for bulk CMOS can be easily modified for FD-SOI. The cost of modification between bulk CMOS and FD-SOI is approximately 10% of that required to migrate to a new technology node for bulk CMOS at 20nm.
An ecosystem needs to be set up for FD-SOI, and it is important for the electronics industry that this ecosystem is established.
There are many advantages for FD-SOI to be widely adopted for high volume, low cost, and lower power applications in the future. It is important for the semiconductor industry to be willing to make investments to provide optimum solutions to its customers rather than follow the roadmap of a specific company. The fabless companies need to be proactive in supporting the supply chain within an FD-SOI ecosystem.
Timing of the migration to 20nm, 14nm, and 10nm technology nodes need to be based on cost, power consumption, and performance metrics that can be easily verified. Being short-term focused and not willing to adopt new concepts can have large cost penalties within the foundry-fabless environment.
FD-SOI technology can be viable in many applications for the next ten years. The semiconductor industry needs to be willing to make the investments for the future rather than responding to short-term pressures.
Cost penalties resulting from very high design costs and long time-to-market can have a serious impact on the competitiveness of semiconductor vendors that select the FinFET approach at 14/16nm. Semiconductor companies that are participating in fast-moving markets cannot tolerate the additional costs of design and long time-to-market associated with trying to fine-tune technologies that are inherently high cost.
While migration to FinFETs may be required beyond the 10nm node, until then FD-SOI represents the best approach for many of the high volume segments of the semiconductor industry.
The reality is that the foundry vendors will not invest unless they have a high probability of getting customers. This means that the customers need to provide the leadership and accept that the present roadmaps in the industry will not provide them with the best financial returns.