FD-SOI: Back to Basics for Best Cost, Energy Efficiency and Performance

By Bich-Yen Nguyen and Christophe Maleville (Soitec)

We are in the era of mobile computing with smart handheld devices and remote data storage “in the cloud,” with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life.  With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer market.

The fully-depleted SOI device/circuit is a unique option that can satisfy all these requirements. Here’s how.

Demonstrated benefits

Planar FD-SOI benefits have been demonstrated by industry and researchers:

  • Better immunity to short channel effects
  • Lowest threshold voltage variation (because random doping fluctuation (RDF) is minimized, enabling a low operation voltage and improving the SRAM and analog mismatch)
  • Low leakage and effective capacitance
  • Better reliability

Very importantly: multiple threshold voltage (VT) capability [1]. FD-SOI devices on ultra-thin BOX (UTBOX), as shown in Figure 1, address a major challenge of the undoped channel devices requirement for SoC applications.


Figure 1: Planar FD0SOI structure

(Courtesy: STMicroelectronics)

Simple FD-SOI Fabrication: Back to Basics

Starting at the 90nm node, to meet the performance, power and density needed to stay on track with Moore’s Law, the process complexity of integrated circuit fabrication has steadily increased. The adoption of new materials, new process/tools and lately new device architecture such as FinFET has resulted in a tremendous increase in wafer processing cost and design cost to extend the life of the bulk MOSFET.

In contrast, planar FD-SOI is simply fabricated with the basic front-end modules: trench isolation, well implants (for ground plane (GP)), gate stack, and source/drain with existing manufacturing CMOS processes.

Moreover, to provide multi-Vt capability for better trade-off of performance and power in bulk devices, both planar and FinFET require additional masks and processes for Vt tuning. The heavy channel doping resulted in large Vt variation due to RDF.  Planar FD-SOI on thin buried oxide (BOX), on the other hand, uses the combination of the work function of the front gate (defined by the metal gate stack) and ground plane (implanted under the box) for tuning Vt. The undoped nature of the FD-SOI channel is retained after the GP implant and the excellent thickness uniformity of the thin silicon film (1nm range) resulted in a lowest Vt variation.

The back bias is a unique feature of this device for ultimate Vt tuning, which further improves SOC energy-efficiency for mobile communications. The FD-SOI process saves several masks and process steps for Vt tuning. It also eliminates the additional masks and the processes needed to build-in the uniaxial stressors for boosting performance in planar and FinFET bulk [4,5].

As a result of integration simplification, Figure 2 shows FD-SOI charting a cost-effective manufacturing path to develop high-performance and lower-power CMOS technology for 28nm and beyond.


Figure 2: FD-SOI vs. Bulk CMOS & FinFET for performance and cost

(Source: Soitec research)

A second generation of 28nm FD-SOI, which implements source/drain engineering, delivers a 25% performance gain over the high-end 28nm high-K/metal gate (HKMG) bulk with slightly lower process wafer cost, or achieve the same performance as 20nm bulk but at the cost of 28nm HKMG. This new generation uses in-situ boron doped SiGe epi for PMOS and phosphorus or arsenide  doped Si or Si(C) Epi for NMOS, as well as forward back bias. Note that this is source/drain engineering – the channel remains undoped, so the advantage of FD-SOI in terms of avoiding RDF is maintained.

The 14nm planar FD-SOI can provide at least the same performance as 14/16nm FinFET-Bulk [7,8], but with much lower total processed wafer cost: approximately 20% lower.  STMicroelectronics has demonstrated, as shown in Figure 3, the performance versus total power comparison for 28nm FD-SOI versus bulk low power (LP) technology. The results show the 28nm FD-SOI with FBB achieved either 35% improved performance at the same total power or 49% total power saving with the same performance. [5]


Figure 3: Performance and Power benchmarking for 28nm FD-SOI vs. Bulk

(Courtesy: STMicroelectronics, ISSCC)

FD-SOI Scalability:  Revolutionary change

FD-SOI is an evolutionary innovation because it has the advantage of being a planar transistor that can use the existing design and EDA tools for early time to market. It is a cost-effective solution for consumer electronic applications.

Figures 4 and 5 describe the FD-SOI technology roadmap, design rule, device architecture and key processes/materials for 3 nodes: 28, 14 and 10nm, respectively [4,8].


Figure 4: FD SOI roadmap

(Courtesy: ST, Leti)


Figure 5: FD-SOI Device Integration for 3 generations: 28, 14 and 10nm

(Source: Soitec)

As FD-SOI technology scales, it is still able to meet density/area, performance and power saving requirements with the same device architecture, standard process module and silicon-based channel material and substrate. Thanks to the non-disruption nature of its change, the simplicity of the process integration and the excellent control of the thin silicon and BOX thickness, the processed wafer cost added per node is much lower than those of the other disruptive device/material changes currently proposed for SoC mobile and consumer applications.

FD-SOI uses the same EDA flow and design techniques as planar bulk, offering a low risk design and manufacturing path for extending Moore’s Law.  The industry’s first Fully-Depleted SOC using 28nm FD-SOI technology was demonstrated by STM/STE with 3GHz performance using low cost 28nm process [4,5]. 15 design-wins with 28nm FD-SOI have been announced by STM for different markets including consumer and networking, with more design wins in the pipeline [9].

In addition, FD-SOI devices with back bias can operate at voltages as low as 0.35V [5,10] without the area and cost penalties caused by the design complexity incurred in bulk devices. This makes FD-SOI technology an extremely attractive option for enabling the Internet of Things.

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1.   O. Weber et. al., ” High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding”, in Proceedings of the IEDM 2008

2.   O. Weber et. al., “Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX” in Proceedings of the IEDM 2010

3.   F. Andieu et. al. “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond“, in Proceedings of the Symposium on VLSI Technology (2010)

4.   J. Hartmann, “Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs”, Fully Depleted Transistors Technology Symposium, December 10, 2012 – San Francisco. See                         http://www.soiconsortium.org/fully-depleted-soi/presentations/december-2012/

5.   P. Flatresse, in Proceedings of the SOI Short Course, S3S Conference, Monterey, October 2013

6.   Q. Liu et. al., “High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond” in Proceedings of the IEDM (2013)

7.   A. Khakifizoor et. al., “Strain Engineered Extremely Thin SOI (ETSOI) for High-Performance CMOS” in Proceedings of the Symposium on VLSI Technology (2012)

8.   L. Grenouillet et. al., “UTBB FDSOI scaling enablers for the 10nm node “, in Proceedings of the S3S Conference, Monterey, October 2013

9.   J. M. Chery PR

10.   H. Makiyama et. Al,Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation” in Proceedings of the IEDM (2013)  

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