By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)
The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as much calculating power as multi-million-dollar supercomputer 10 years ago! But at 28nm, it seems the race is over: Moore’s scaling is facing obstacles – parasitic phenomena, incompressible delays, energy dissipation – that can be overcome with technology, but not in a way that is economically sustainable for everyone. This is where the idea to go 3D comes in: the density and cost dictated by Moore’s Law would be achieved not by 2D shrinking but by going up into the third dimension.
Piling transistors on top of each other in a “3D” configuration is not new. Stacking techniques using through-silicon vias (TSVs) are currently used for CMOS image sensors, MEMS, and now 3DNAND. In these scenarios, the devices themselves are processed on separate wafers, then aligned and bonded. The TSVs are essentially copper columns added to connect the top and bottom devices. While beneficial in certain cases, the TSV approach faces its own set of challenges with respect to aligning the transistors, the comparatively wide diameters of the TSVs, the pitch and the overall thickness.
Monolithic 3D (M3D), which takes a very different approach to stacking transistors on top of each other, is one of the most promising alternatives approaches when going 3D. M3D aims at increasing transistor density “sequentially” – meaning within a single process flow, as opposed to the TSV approach, which is applied to die that have already been processed. Staying within the bounds of a single process flow makes M3D much more cost-effective. M3D will enable an increased density of transistors without requiring the downscaling of their individual features. M3D could also provide a gain in performance by reducing the metal wiring delay, thanks to direct contact between transistor levels. From a cost perspective, M3D appears to offer a competitive advantage over equivalent N+1 scaling nodes: the scaling achieved in node N and even N-1 can be leveraged for another generation.
At CEA-Leti in Grenoble (France), one of the world’s most advanced microelectronics R&D centers, CMOS-device teams are exploring various routes to meet increased performance requirements of future semiconductor applications. M3D is a primary focus in the search for alternate routes to scaling, in addition to other disruptive approaches such as steep slope devices, mechanical switches based on NEMS and single electron transistors.
Leti is known for its expertise in the fields needed to demonstrate and take the industry lead in the M3D concept:
- a strong background-related to SOI devices fabrication
- a long history of process developments in molecular bonding of various substrates and materials, essential for creating a high-quality top active layer
- thorough experience in 3D stacking techniques, including design-tool developments, architecture exploration and test-vehicle or full-circuit implementations.
Leti’s M3D program was first launched in 2007. In order to reach the expected performance with an acceptable time to market, M3D must be developed with close, simultaneous attention to applications, design and technology challenges. The success demonstrated since the program launch prompted Qualcomm to partner with Leti in 2014 to explore M3D technology potential for future generations of products.
Leti’s M3D: How it’s done
The M3D concept consists of sequentially processing:
- processing a bottom MOS transistor layer
- processing another MOS transistor layer on top of the bottom one with lithographic alignment between the layers
- positioning metal lines between the two layers to allow connections between both transistor levels.
- encapsulating the inter-metal levels in an oxide layer
- bonding a wafer substrate to the top transistor layer using molecular bonding
- a planarization process.
Using an SOI wafer for the top layer molecular bonding provides higher crystalline quality, greater integration density, and accurate thickness control. CEA-Leti has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.
The main advantages of M3D are derived from the sequential fabrication of the various transistor layers on the same wafer. It leads to very high alignment accuracy (3D contact pitch <100nm using lithography tools adapted to 14nm production), uses high-density interconnects, and surpasses 3D-TSV performance at a competitive cost. The inter-metal levels also facilitate design partitioning and architecture exploration.
Leti’s M3D approach is of particularly high value for those products that do not really benefit from scaling, especially when cost constraints are stringent. Different design simulations estimate a gain of one-node performance without scaling constraints. Once the remaining challenges are overcome, potential applications range from heterogeneous stacks (imagers, MEMS on logic) to advanced memory structures, advanced processors, programmable logic and various SOCs. All those products would benefit greatly from the added value provided by M3D:
- High-circuit density provided by stacking active layers in 3D at minimum-contact pitch level
- Better power dissipation (greater absorption across inter-metal levels surface)
- Increased speed/power performance trade-off by reducing high-resistivity metal wiring length.
- Competitive cost advantage by re-using a given node process scheme without requiring additional/new steps to achieve performance gains.
PDK & Model Availability
In addition to the M3D technology process flow development, CEA-Leti is also proposing a Predictive Design Kit (PDK) that provides a primitive M3D product design environment for integrated modeling, simulation, visualization and communication. It also includes validation tools that product designers need to benchmark M3D and explore new architecture concepts. The first M3D PDK version available from CEA-Leti will permit partners to get a first knowledge of the M3D technology, so they can run initial performance assessments regarding density, speed, power and cost.
Part of CEA-Leti’s mission is to develop technologies that are ready to transfer to industry, supporting customers in both developing knowledge and implementation on the manufacturing floor. In the case of M3D, CEA-Leti is beginning to build a full ecosystem of partners to enable the rapid industrialization of this technology. Qualcomm, a world leader in wireless technologies, joined CEA-Leti in its M3D R&D program in 2014 and has committed resources to assess the feasibility of the concept.
To expand the momentum around M3D, while validating design-and-process assumptions and expected performance through prototyping demonstrators, the ecosystem should also involve a major foundry. CEA-Leti also plans to include additional members of the semiconductor business value chain (device modeling, EDA, process tooling, test, etc.) to form a complete M3D ecosystem, and make M3D a competitive technology for industrial transfer.
In the short term, CEA-Leti is looking for interested companies to engage in an R&D program aimed at validating proof of concept of an M3D integration process flow and its related libraries for advanced CMOS nodes.
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- P.Batude et al – 3D Monolithic Integration, IEEE 2011
- P.Batude et al – 3-D Sequential Integration: a Key Enabling Technology for Heterogeneous Co-Integration of New function with CMOS, IEEE Journal on Emerging and selected topics in Circuits & Systems, 2012
- S.Bobba et al – CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits, IEEE 2011
- O. Turkyilmaz et al – 3D FPGA using high-density interconnect Monolithic Integration, DATE 2014